PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 470

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2480/2580/4480/4580
C
C Compilers
CALL ................................................................................ 376
CALLW ............................................................................. 405
Capture (CCP Module) ..................................................... 165
Capture (ECCP Module) .................................................. 174
Capture/Compare/PWM (CCP) ........................................ 163
Clock Sources .................................................................... 28
Clocking Scheme/Instruction Cycle .................................... 65
CLRF ................................................................................ 377
CLRWDT .......................................................................... 377
Code Examples
Code Protection ............................................................... 343
DS39637A-page 468
MPLAB C17 ............................................................. 412
MPLAB C18 ............................................................. 412
MPLAB C30 ............................................................. 412
Associated Registers ............................................... 168
CCP Pin Configuration ............................................. 165
Software Interrupt .................................................... 165
Timer1/Timer3 Mode Selection ................................ 165
ECCPR1H:ECCPR1L Registers .............................. 165
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................ 164
CCPRxH Register .................................................... 164
CCPRxL Register ..................................................... 164
Compare Mode. See Compare.
Interaction Between CCP1 and ECCP1
Module Configuration ............................................... 164
PWM Mode. See PWM.
Selecting the 31 kHz Source ...................................... 29
Selection Using OSCCON Register ........................... 29
16 x 16 Signed Multiply Routine .............................. 112
16 x 16 Unsigned Multiply Routine .......................... 112
8 x 8 Signed Multiply Routine .................................. 111
8 x 8 Unsigned Multiply Routine .............................. 111
Changing Between Capture Prescalers ................... 165
Changing to Configuration Mode ............................. 278
Computed GOTO Using an Offset Value ................... 64
Data EEPROM Read ............................................... 107
Data EEPROM Refresh Routine .............................. 108
Data EEPROM Write ............................................... 107
Erasing a Flash Program Memory Row ................... 100
Fast Register Stack .................................................... 64
How to Clear RAM (Bank 1) Using
Implementing a Real-Time Clock Using a
Initializing PORTA .................................................... 129
Initializing PORTB .................................................... 132
Initializing PORTC .................................................... 135
Initializing PORTD .................................................... 138
Initializing PORTE .................................................... 141
Loading the SSPBUF (SSPSR) Register ................. 190
Reading a CAN Message ........................................ 293
Reading a Flash Program Memory Word .................. 99
Saving Status, WREG and
Transmitting a CAN Message Using
Transmitting a CAN Message Using WIN Bits ......... 286
WIN and ICODE Bits Usage in Interrupt Service
Writing to Flash Program Memory ................... 102–103
for Timer Resources ........................................ 164
Indirect Addressing ............................................ 89
Timer1 Interrupt Service .................................. 155
BSR Registers in RAM ..................................... 128
Banked Method ................................................ 286
Routine to Access TX/RX Buffers .................... 278
Preliminary
COMF .............................................................................. 378
Comparator ...................................................................... 257
Comparator Specifications ............................................... 430
Comparator Voltage Reference ....................................... 263
Compare (CCP Module) .................................................. 167
Compare (CCP1 Module)
Compare (ECCP Module) ................................................ 174
Configuration Bits ............................................................ 343
Configuration Mode ......................................................... 324
Configuration Register Protection .................................... 360
Context Saving During Interrupts ..................................... 128
Conversion Considerations .............................................. 464
CPFSEQ .......................................................................... 378
CPFSGT .......................................................................... 379
CPFSLT ........................................................................... 379
Crystal Oscillator/Ceramic Resonator ................................ 23
D
Data Addressing Modes .................................................... 89
Data EEPROM Code Protection ...................................... 360
Data EEPROM Memory ................................................... 105
Analog Input Connection Considerations ................ 261
Associated Registers ............................................... 261
Configuration ........................................................... 258
Effects of a Reset .................................................... 260
Interrupts ................................................................. 260
Operation ................................................................. 259
Operation During Sleep ........................................... 260
Outputs .................................................................... 259
Reference ................................................................ 259
Response Time ........................................................ 259
Accuracy and Error .................................................. 264
Associated Registers ............................................... 265
Configuring .............................................................. 263
Connection Considerations ...................................... 264
Effects of a Reset .................................................... 264
Operation During Sleep ........................................... 264
Associated Registers ............................................... 168
CCP Pin Configuration ............................................. 167
CCPR1 Register ...................................................... 167
Software Interrupt .................................................... 167
Special Event Trigger ...................................... 161, 167
Timer1/Timer3 Mode Selection ................................ 167
Special Event Trigger .............................................. 256
Special Event Trigger .............................................. 174
Comparing Addressing Modes with the
Direct ......................................................................... 89
Indexed Literal Offset ................................................ 92
Indirect ....................................................................... 89
Inherent and Literal .................................................... 89
Associated Registers ............................................... 109
EEADR Register ...................................................... 105
EECON1 and EECON2 Registers ........................... 105
Operation During Code-Protect ............................... 108
Protection Against Spurious Write ........................... 108
Reading ................................................................... 107
Using ....................................................................... 108
Write Verify .............................................................. 107
Writing ..................................................................... 107
External Signal ................................................ 259
Internal Signal .................................................. 259
Extended Instruction Set Enabled ..................... 93
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