PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 411

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

ADDWF
Syntax:
Operands:
Operation:
Status Affected: N, OV, C, DC, Z
Encoding:
Description:
Words:
Cycles:
Example:
 2004 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
OFST
FSR2
Contents
of 0A2Ch
W
Contents
of 0A2Ch
Q1
(W) + ((FSR2) + k)
ADD W to Indexed
(Indexed Literal Offset mode)
ADDWF
0
d
a
The contents of W are added to the contents
of the register indicated by FSR2, offset by the
value ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’ (default).
1
1
0010
0
k
[0,1]
ADDWF
Read ‘k’
95
Q2
[k] {,d}
=
=
=
=
=
=
01d0
[OFST] ,0
Process
17h
2Ch
0A00h
20h
37h
20h
Data
dest
Q3
kkkk
destination
Write to
PIC18F2480/2580/4480/4580
Q4
kkkk
Preliminary
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
Decode
FLAG_OFST
FSR2
Contents
of 0A0Ah
Contents
of 0A0Ah
OFST
FSR2
Contents
of 0A2Ch
Contents
of 0A2Ch
Q1
Q1
register ‘f’
Bit Set Indexed
(Indexed Literal Offset mode)
BSF [k], b
0
0
a = 0
1
None
Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
1
1
BSF
Set Indexed
(Indexed Literal Offset mode)
SETF [k]
0
FFh
None
The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
1
1
Read ‘k’
SETF
Read
1000
0110
Q2
Q2
=
=
=
=
f
b
k
((FSR2 + k))<b>
95
95
7
((FSR2) + k)
=
=
=
=
2Ch
0A00h
00h
FFh
[FLAG_OFST], 7
[OFST]
bbb0
1000
Process
0Ah
0A00h
55h
D5h
Process
Data
Data
Q3
Q3
DS39637A-page 409
kkkk
kkkk
destination
Write to
register
Write
Q4
Q4
kkkk
kkkk