PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 359

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

24.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainder
of the memory is divided into four blocks on binary
boundaries.
FIGURE 24-5:
 2004 Microchip Technology Inc.
000000h
0007FFh
000800h
000FFFh
001000h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
008000h
1FFFFFh
Address
Range
BBSIZ
Program Verification and
Code Protection
®
devices.
Unimplemented
Boot Block
Read ‘0’s
Block 0
Block 1
Block 2
Block 3
1 KW
3 KW
4 KW
4 KW
4 KW
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2480/2580/4480/4580
0
(PIC18F2580/4580)
32 Kbytes
Unimplemented
Boot Block
Read ‘0’s
Block 0
Block 1
Block 2
Block 3
MEMORY SIZE/DEVICE
2 KW
2 KW
4 KW
4 KW
4 KW
1
PIC18F2480/2580/4480/4580
Unimplemented
Preliminary
Boot Block
Read ‘0’s
Block 0
Block 1
1 KW
3 KW
4 KW
0
(PIC18F2480/4480)
16 Kbytes
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 24-5 shows the program memory organization
for 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
Unimplemented
Boot Block
Read ‘0’s
Block 0
Block 1
2 KW
2 KW
4 KW
1
(Unimplemented Memory Space)
Block Code Protection
CPB, WRTB, EBRTB
CP3, WRT3, EBTR3
CP0, WRT0, EBRT0
CP2, WRT2, EBRT2
CP!, WRT1, EBRT1
Controlled by:
(Boot Block)
(Block 0)
(Block 1)
(Block 2)
(Block 3)
DS39637A-page 357