PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 222

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2480/2580/4480/4580
17.4.12
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (T
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for T
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 17-23).
17.4.12.1
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 17-23:
FIGURE 17-24:
DS39637A-page 220
ACKNOWLEDGE SEQUENCE
TIMING
WCOL Status Flag
SSPIF
Note: T
SCL
SDA
Note: T
sequence
SDA
Acknowledge sequence starts here,
SCL
Write to SSPCON2,
Falling edge of
9th clock
BRG
BRG
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
ACK
= one Baud Rate Generator period.
= one Baud Rate Generator period.
ACKEN = 1, ACKDT = 0
Set SSPIF at the
end of receive
BRG
set PEN
enable
write to SSPCON2
. The SCL pin is then
SDA asserted low before rising edge of clock
to setup Stop condition
8
bit,
D0
T
T
BRG
BRG
ACKEN
BRG
Preliminary
T
SCL brought high after T
BRG
)
Cleared in
software
T
BRG
P
ACK
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set.
T
BRG
17.4.13
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the Baud Rate Generator is reloaded and
counts down to ‘0’. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
T
SDA pin will be deasserted. When the SDA pin is
sampled high while SCL is high, the P bit
(SSPSTAT<4>) is set. A T
cleared and the SSPIF bit is set (Figure 17-24).
17.4.13.1
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
BRG
T
BRG
9
Set SSPIF at the end
of Acknowledge sequence
(Baud Rate Generator rollover count) later, the
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
BRG
BRG
, followed by SDA = 1 for T
STOP CONDITION TIMING
ACKEN automatically cleared
WCOL Status Flag
Cleared in
software
 2004 Microchip Technology Inc.
BRG
BRG
later, the PEN bit is