PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 453
PIC18F2480
Manufacturer Part Number
PIC18F2480
Description
28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F2480.pdf
(484 pages)
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FIGURE 27-22:
TABLE 27-25: A/D CONVERSION REQUIREMENTS
2004 Microchip Technology Inc.
130
131
132
135
136
Note 1:
Param
No.
A/D DATA
Note 1:
SAMPLE
A/D CLK
2:
3:
4:
5:
ADRES
BSF ADCON0, GO
T
T
T
T
T
Symbol
ADIF
AD
CNV
ACQ
SWC
AMP
GO
Q4
2:
The time of the A/D clock period is dependent on the device frequency and the T
ADRES register may be read on the following T
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AV
50 .
On the following cycle of the device clock.
See Section 19.0 “10-Bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when input
voltage has changed more than 1 LSb.
If the A/D clock source is selected as RC, a time of T
This allows the SLEEP instruction to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
132
A/D Clock Period
Conversion Time
(not including acquisition time) (Note 2)
Acquisition Time (Note 3)
Switching Time from Convert
Amplifier Settling Time (Note 5)
A/D CONVERSION TIMING
Characteristic
(Note 2)
9
DD
to AV
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
8
SS
PIC18F2480/2580/4480/4580
OLD_DATA
or AV
7
Sample
Preliminary
SS
. . .
SAMPLING STOPPED
to AV
CY
is added before the A/D clock starts.
CY
Min
1.6
3.0
2.0
3.0
15
10
11
—
DD
. . .
1
131
130
cycle.
). The source impedance (R
(Note 4)
2
20
20
Max
6.0
9.0
12
—
—
—
(1)
(1)
1
Units
T
—
AD
s
s
s
s
s
s
s
T
V
T
A/D RC mode
V
A/D RC mode
-40 C to +85 C
This may be used if the “new” input
voltage has not changed by more
than 1 LSb (i.e., 5 mV @ 5.12V)
from the last sampled voltage (as
stated on C
0 C
OSC
OSC
DD
DD
0
= 2.0V;
= 2.0V;
based, V
based, V
S
to
AD
) on the input channels is
clock divider.
NEW_DATA
DONE
Conditions
HOLD
+85 C
DS39637A-page 451
REF
REF
).
T
CY
full range
3.0V
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