MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 104
MC68HC912BD32CFU10
Manufacturer Part Number
MC68HC912BD32CFU10
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC68HC912BD32CFU10.pdf
(292 pages)
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SLOW — Slow Mode Divider Register
Slow Mode Divider
CGM Register Description
Clocks
MC68HC912BD32 Rev 1.0
RESET:
Bit 7
NOTE:
0
0
6
0
0
The slow mode divider is included to deliver a variable bus frequency to
the MCU in wait mode. The bus clocks are derived from the constant P
clock. The slow clock counter divides the P clock and E clock frequency
in powers of 2, up to 128. When the slow control register is cleared or
the part is not in wait mode, the slow mode divider is off and the bus
clocks frequency is not changed.
The clock monitor is clocked by the system clock (oscillator) reference;
the slow mode divider allows operation of the MCU at clock periods
longer than the clock monitor trigger time.
SLDV2–SLDV0 — Slow Mode Divisor Selector Bits
The value 2 raised to the power indicated by these three bits, produce
the slow mode frequency divider. The range of the divider is 2 to 128
by steps of power of 2. When the bits are clear, the divider is
bypassed.
resulting bus rate for three example oscillator frequencies.
Freescale Semiconductor, Inc.
For More Information On This Product,
5
0
0
Go to: www.freescale.com
Figure 19
4
0
0
Clocks
shows the divider for all bit conditions and the
3
0
0
SLDV2
2
0
SLDV1
1
0
SLDV0
Bit 0
0
$00E0
4-clock
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