MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 142

• Manufacturer Part Number: MC68HC912BD32CFU10
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

PACTL — Pulse Accumulator Control Register
Standard Timer Module
MC68HC912BD32 Rev 1.0
RESET:
Bit 7
0
0
PAEN
6
0
PAEN — Pulse Accumulator System Enable
PAMOD — Pulse Accumulator Mode
PEDGE — Pulse Accumulator Edge Control
Depending on the TIOS bit for the corresponding channel, these
registers are used to latch the value of the free-running counter when
a defined transition is sensed by the corresponding input capture
edge detector or to trigger an output action for output compare.
Read anytime. Write anytime for output compare function. Writes to
these registers have no meaning or effect during input capture. All
timer input capture/output compare registers are reset to $0000.
Read or write anytime.
PAEN is independent from TEN.
For PAMOD = 0 (event counter mode)
For PAMOD = 1 (gated time accumulation mode)
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0 = Pulse Accumulator system disabled
1 = Pulse Accumulator system enabled
0 = Event counter mode
1 = Gated time accumulation mode
0 = Falling edges on the pulse accumulator input pin (PT7/PAI)
1 = Rising edges on the pulse accumulator input pin cause the
0 = Pulse accumulator input pin high enables E 64 clock to pulse
1 = Pulse accumulator input pin low enables E 64 clock to pulse
PAMOD
5
0
cause the count to be incremented
count to be incremented
accumulator and the trailing falling edge on the pulse
accumulator input pin sets the PAIF flag.
accumulator and the trailing rising edge on the pulse
accumulator input pin sets the PAIF flag.
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Standard Timer Module
PEDGE
4
0
CLK1
3
0
CLK0
2
0
PAOVI
1
0
Bit 0
PAI
0
$00A0
12-timer