MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 155

• Manufacturer Part Number: MC68HC912BD32CFU10
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

SC0SR1 — SCI Status Register 1
9-sint
RESET:
TDRE
Bit 7
1
TC
6
1
TE — Transmitter Enable
RE — Receiver Enable
RWU — Receiver Wake-Up Control
SBK — Send Break
As long as SBK remains set the transmitter will send zeros. When
SBK is changed to zero, the current frame of all zeros is finished
before the TxD line goes to the idle state. If SBK is toggled on and off,
the transmitter will send 10 (or 11) zeros and then revert to mark idle
or sending data.
The bits in these registers are set by various conditions in the SCI
hardware and are automatically cleared by special acknowledge
sequences. The receive related flag bits in SC0SR1 (RDRF, IDLE,
OR, NF, FE, and PF) are all cleared by a read of the SC0SR1 register
followed by a read of the transmit/receive data register L. However,
only those bits which were set when SC0SR1 was read will be cleared
by the subsequent read of the transmit/receive data register L. The
Freescale Semiconductor, Inc.
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0 = Transmitter disabled
1 = SCI transmit logic is enabled and the TXD pin (Port S bit 1) is
0 = Receiver disabled
1 = Enables the SCI receive circuitry
0 = Normal SCI Receiver
1 = Enables the wake-up function and inhibits further receiver
0 = Break generator off
1 = Generate a break code (at least 10 or 11 contiguous zeros)
RDRF
5
0
dedicated to the transmitter. The TE bit can be used to queue
an idle preamble.
interrupts. Normally hardware wakes the receiver by
automatically clearing this bit.
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IDLE
Serial Interface
4
0
OR
3
0
NF
2
0
Serial Communication Interface (SCI)
FE
1
0
MC68HC912BD32 Rev 1.0
Bit 0
PF
0
Serial Interface
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