MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 97

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MC68HC912BD32CFU10

Manufacturer Part Number
MC68HC912BD32CFU10
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
HPRIO — Highest Priority I Interrupt
Resets
Power-On Reset
External Reset
5-resets
RESET:
Bit 7
1
1
Write only if I mask in CCR = 1 (interrupts inhibited). Read anytime.
To give a maskable interrupt source highest priority, write the low byte
of the vector address to the HPRIO register. For example, writing $F0 to
HPRIO would assign highest maskable interrupt priority to the real-time
interrupt timer ($FFF0). If an unimplemented vector address or a
non-I-masked vector address (value higher than $F2) is written, then
IRQ will be the default highest priority interrupt.
There are four possible sources of reset. Power-on reset (POR), and
external reset on the RESET pin share the normal reset vector. The
computer operating properly (COP) reset and the clock monitor reset
each has a vector. Entry into reset is asynchronous and does not require
a clock but the MCU cannot sequence out of reset without a system
clock.
A positive transition on V
voltage level detector, or other external reset circuits, are the usual
source of reset in a system. The POR circuit only initializes internal
circuitry during cold starts and cannot be used to force a reset as system
voltage drops.
The CPU distinguishes between internal and external reset conditions
by sensing whether the reset pin rises to a logic one in less than eight
E-clock cycles after an internal device releases reset. When a reset
condition is sensed, the RESET pin is driven low by an internal device
for about 16 E-clock cycles, then released. Eight E-clock cycles later it
is sampled. If the pin is still held low, the CPU assumes that an external
Freescale Semiconductor, Inc.
6
1
1
For More Information On This Product,
PSEL5
Go to: www.freescale.com
5
1
Resets and Interrupts
PSEL4
4
1
DD
causes a power-on reset (POR). An external
PSEL3
3
0
PSEL2
2
0
MC68HC912BD32 Rev 1.0
PSEL1
1
1
Resets and Interrupts
Bit 0
0
0
$001F
Resets

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