MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 98

• Manufacturer Part Number: MC68HC912BD32CFU10
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

COP Reset
Clock Monitor
Reset
Effects of Reset
Operating Mode
and Memory Map
Resets and Interrupts
MC68HC912BD32 Rev 1.0
reset has occurred. If the pin is high, it indicates that the reset was
initiated internally by either the COP system or the clock monitor.
To prevent a COP or clock monitor reset from being detected during an
external reset, hold the reset pin low for at least 32 cycles. An external
RC power-up delay circuit on the reset pin is not recommended — circuit
charge time can cause the MCU to misinterpret the type of reset that has
occurred.
The MCU includes a computer operating properly (COP) system to help
protect against software failures. When COP is enabled, software must
write $55 and $AA (in this order) to the COPRST register in order to keep
a watchdog timer from timing out. Other instructions may be executed
between these writes. A write of any value other than $55 or $AA or
software failing to execute the sequence properly causes a COP reset
to occur.
If clock frequency falls below a predetermined limit when the clock
monitor is enabled, a reset occurs.
When a reset occurs, MCU registers and control bits are changed to
known start-up states, as follows.
Operating mode and default memory mapping are determined by the
states of the BKGD, MODA, and MODB pins during reset. The SMODN,
MODA, and MODB bits in the MODE register reflect the status of the
mode-select inputs at the rising edge of reset. Operating mode and
default maps can subsequently be changed according to strictly defined
rules.
Freescale Semiconductor, Inc.
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Resets and Interrupts
6-resets