MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 164

• Manufacturer Part Number: MC68HC912BD32CFU10
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

SP0CR1 — SPI Control Register 1
Serial Interface
MC68HC912BD32 Rev 1.0
RESET:
SPIE
Bit 7
0
SPE
6
0
SPIE — SPI Interrupt Enable
SPE — SPI System Enable
SWOM — Port S Wired-OR Mode
MSTR — SPI Master/Slave Mode Select
CPOL, CPHA — SPI Clock Polarity, Clock Phase
SSOE — Slave Select Output Enable
Read or write anytime.
When MODF is set, SPE always reads zero. SP0CR1 must be written
as part of a mode fault recovery sequence.
Controls not only SPI output pins but also the general-purpose output
pins (PS[4:7]) which are not used by SPI.
These two bits are used to specify the clock format to be used in SPI
operations. When the clock polarity bit is cleared and data is not being
transferred, the SCK pin of the master device is low. When CPOL is
set, SCK idles high. See
The SS output feature is enabled only in the master mode by
asserting the SSOE and DDS7.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Hardware interrupt sequence is requested each time the SPIF
0 = SPI interrupts are inhibited
0 = SPI internal hardware is initialized and SPI system is in a
1 = PS[4:7] are dedicated to the SPI function
0 = SPI and/or PS[4:7] output buffers operate normally
1 = SPI and/or PS[4:7] output buffers behave as open-drain
0 = Slave mode
1 = Master mode
SWOM
5
0
or MODF status flag is set
low-power disabled state.
outputs
Go to: www.freescale.com
MSTR
Serial Interface
4
0
CPOL
Figure 22
3
0
CPHA
2
1
and
Figure
SSOE
1
0
23.
LSBF
Bit 0
0
$00D0
18-sint