MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 126

• Manufacturer Part Number: MC68HC912BD32CFU10
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

PWCTL— PWM Control Register
Pulse Width Modulator
MC68HC912BD32 Rev 1.0
RESET:
Bit 7
0
0
Left-Aligned-Output Mode (CENTR = 0):
Duty cycle = [(PWDTYx
Duty cycle = [(PWPERx PWDTYx) (PWPERx 1)] 100%(PPOLx =
0)
Center-Aligned-Output Mode (CENTR = 1):
Duty cycle = [(PWPERx
Duty cycle = (PWDTYx) (PWPERx)
PSWAI — PWM Halts while in Wait Mode
CENTR — Center-Aligned Output Mode
RDP — Reduced Drive of Port P
PUPP — Pull-Up Port P Enable
Read and write anytime.
Program change of CENTR bit should be done when PWM channels
are disabled. All PWM counters should be written to as the last
operation before enabling the channels. Otherwise,
asserting/de-asserting the CENTR bit may cause irregularities in the
PWM output.
Freescale Semiconductor, Inc.
6
0
0
For More Information On This Product,
0 = Allows PWM main clock generator to continue while in Wait
1 = Halt PWM main clock generator when the part is in Wait mode.
0 = PWM channels operate in Left-Aligned Output mode
1 = PWM channels operate in Center-Aligned Output mode
0 = All port P output pins have normal drive capability.
1 = All port P output pins have reduced drive capability.
0 = All port P pins have an active pull-up device disabled.
1 = All port P pins have an active pull-up device enabled.
mode.
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5
0
0
Pulse Width Modulator
PSWAI
4
0
1) (PWPERx
PWDTYx) PWPERx]
CENTR
3
0
100%(PPOLx = 0)
RDP
2
0
1)]
100% (PPOLx = 1)
PUPP
100% (PPOLx = 1)
1
0
PSBCK
Bit 0
0
$0054
14-pwm