MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 182

• Manufacturer Part Number: MC68HC912BD32CFU10
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Receive FIFO
Function
Byteflight™ Module
MC68HC912BD32 Rev 1.0
NOTE:
Bit manipulation instructions (BSET or BCLR) shall not be used to clear
interrupt flags.
A part or all of the message buffers can be configured to a Receive
First-In-First-Out (FIFO) System, which can be used as logic analyzer
buffers or for receiving consecutive data streams.
The FIFO starts with message buffer 0 and can be configured to the
maximum of all 16 message buffers. Every incoming message not
matching with any receive identifier but matching the programmable
FIFO filter is stored into the FIFO buffer system. A status bit shows that
the Receive FIFO is not empty, another status bit shows that a Receive
FIFO Overrun has been detected. If enabled, interrupts are generated.
There are two index registers associated with the FIFO. The PUT Index
Register (PUTIDX) is used as an index to the next available location in
the FIFO buffer system. When a new message has been received it is
written into the buffer addressed by the PUTIDX; the PUTIDX is then
incremented so it addresses the next buffer. If the PUTIDX is
incremented past the highest FIFO message buffer the PUTIDX is reset
to 0. The GET Index Register (GETIDX) is used to address the next
FIFO buffer to be read. The GETIDX is incremented when unlocking the
Receive FIFO buffer. The FIFO buffer system is completely filled, when
the PUT Pointer (PUTIDX) has reached again the value of the GET
Pointer (GETIDX). A new incoming messages cannot be stored into the
FIFO. The FIFO overrun flag is set at the end of this message if no error
has occurred. A Receive FIFO non empty status is detected when the
PUTIDX differs from the GETIDX. This indicates there is at least one
received message in the FIFO buffer system. The PUTIDX and the
GETIDX are not addressable by the CPU.
The FIFO empty, FIFO not empty and the FIFO overrun situations are
explained in
•
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For More Information On This Product,
Clear the IFLG (buffer empty) by writing a ‘1’ to it.
Unlock the message buffer.
Figure 31
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Byteflight™ Module
below for a three buffer FIFO.
12-sibus