MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 76

• Manufacturer Part Number: MC68HC912BD32CFU10
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Read/Write
Accesses During
Program/Erase
Program/Erase
Verification
Program/Erase
Sequence
Flash EEPROM
MC68HC912BD32 Rev 1.0
the entire array if the new value does not require the changing of bit
values from zero to one.
During program or erase operations, read and write accesses may be
different from those during normal operation and are affected by the
state of the control bits in the Flash EEPROM control register (FEECTL).
The next write to any valid address to the array after LAT is set will cause
the address and data to be latched into the programming latches. Once
the address and data are latched, write accesses to the array will be
ignored while LAT is set. Writes to the control registers will occur
normally.
When programming or erasing the Flash EEPROM array, a special
verification method is required to ensure that the program/erase process
is reliable, and also to provide the longest possible life expectancy. This
method requires stopping the program/erase sequence at periods of
t
programmed/erased. After the location reaches the proper value, it must
continue to be programmed/erased with additional margin pulses to
ensure that it will remain programmed/erased. Failure to provide the
margin pulses could lead to corrupted or unreliable data.
To begin a program or erase sequence the external V
applied and stabilized. The ERAS bit must be set or cleared, depending
on whether a program sequence or an erase sequence is to occur. The
LAT bit will be set to cause any subsequent data written to a valid
address within the Flash EEPROM to be latched into the programming
address and data latches. The next Flash array write cycle must be
either to the location that is to be programmed if a programming
sequence is being performed, or, if erasing, to any valid Flash EEPROM
array location. Writing the new address and data information to the Flash
EEPROM is followed by assertion of ENPE to turn on the program/erase
voltage to program/erase the new location(s). The LAT bit must be
asserted and the address and data latched to allow the setting of the
ENPE control bit. If the data and address have not been latched, an
attempt to assert ENPE will be ignored and ENPE will remain negated
after the write cycle to FEECTL is completed. The LAT bit must remain
PPULSE
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EPULSE
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Flash EEPROM
for erasing) to determine if the Flash EEPROM is
FP
voltage must be
8-flash