MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 201

• Manufacturer Part Number: MC68HC912BD32CFU10
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Message Buffer
Control Registers
(BUFCTL15..0)
31-sibus
BUFCTLn
HARDRESET
W
R
Figure 35 Message Buffer Control Registers (BUFCTL15:BUFCTL0)
BIT 7
IFLG
0
Each of the 16 configurable message buffers is associated with one
Buffer Control Register. All 16 registers are addressable by the CPU.
Only a hard reset will clear the register.
CFG — Message Buffer Configuration Bit
BIT 6
IENA
This bit is used to configure the corresponding buffer as transmit
buffer or as receive or receive FIFO buffer. This bit is readable and is
only cleared by hard reset. Writing to this bit is allowed during soft
reset only.
Freescale Semiconductor, Inc.
0
For More Information On This Product,
1 = The corresponding buffer is configured as transmit buffer.
0 = The corresponding buffer is configured as receive buffer or
receive FIFO buffer.
LOCK
Go to: www.freescale.com
BIT 5
0
Figure 34 Message Buffer Organization
$xxxC
$xxxD
$xxxA
$xxxB
$xxxE
$xxxF
$xxx0
$xxx1
$xxx2
$xxx3
$xxx4
$xxx5
$xxx6
$xxx7
$xxx8
$xxx9
Addr
Byteflight™ Module
ABTAK
BIT 4
Data Length Register (4 msb reserved)
0
ABTRQ
Identifier Register
Data Register 10
Data Register 11
BIT 3
Register Name
Data Register 0
Data Register 1
Data Register 2
Data Register 3
Data Register 4
Data Register 5
Data Register 6
Data Register 7
Data Register 8
Data Register 9
0
reserved
reserved
BIT 2
0
0
MC68HC912BD32 Rev 1.0
Programmer’s Model
BIT 1
Byteflight™ Module
0
0
CFG*
BIT 0
0