HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 18

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

REGISTERS, Cont.
Bit No.
15
14-10
9
8
7-4
3
2
1
0
TIME-TAG REGISTER
This register is Read Only and is cleared after
return the current value of the free running 16-bit Time Tag counter. Counter resolution is programmed by TTCK2:0 bits in
Configuration Register 1. Options are: 2, 4, 8, 16, 32 and 64us, or externally provided clock.
The device automatically resets the Time-Tag count when a “synchronize” mode command without data (MC1) is received. In
addition, the host can reset the Time-Tag count at any time by asserting the RTTAG bit in Configuration Register 2.
The MCOPT2 and MCOPT3 bits in Configuration Register 2 allow automatic loading of Time-Tag count using the data word
received with a “synchronize with data” mode command, MC17. If both of these bits equal one, the data word received with a
valid “synchronize” mode command (MC17) is unconditionally loaded into the Time-Tag counter. For non-broadcast MC17
commands, the counter load occurs before status word transmission. If both MCOPT2 and MCOPT3 bits equal 0, the external
host assumes responsibility for actions needed to perform “synchronize” duties upon reception of the valid MC17
“synchronize” command, but status transmission automatically occurs.
MSB
15 14 13 12 11 10 9
15 14 13 12 11 10 9
TXANDCLR Transmit (Once) and Clear.
Mnemonic Status Bit or Function
——
INST
SVCREQ
——
BUSY
SSYSF
——
TF
TIME-TAG COUNT 15:0
When this bit is set, the register is cleared after any set bits 0-9 are used once in a transmitted status
Not used, these bits cannot be set.
Instrumentation.
When this bit is asserted, the Instrumentation status bit is set.
Service Request.
When this bit is asserted, the Service Request status bit is set.
Not used, these bits cannot be set.
Busy (global).
When this bit is asserted, the device asserts Busy bit in status response for all valid commands.
Subsystem Flag.
This register bit is logically ORed with the SSYSF input pin. If either SSYSF register bit or SSYSF pin
Not used, this bit cannot be set.
Terminal Flag.
word. This bit does not affect operation of the Transmit Status Word and Transmit Last Command
mode codes. Example: Transaction of a valid legal command with the INST and TXANDCLR bits
asserted results in status word transmission with the Instrumentation bit set. If the following
command is Transmit Status or Transmit Last Command mode code, the Instrumentation bit remains
set.
Instead of globally enabling Busy status for all commands here, the host can assert Busy status for
selected commands by asserting the Busy bit in descriptor table Control Words for the individual
commands. When response to a command conveys Busy status, the device suppresses
transmission of data words that would normally accompany status transmission. For any message
transacted with Busy status, the WASBUSY flag is asserted in the stored Message Information Word.
is asserted, the SSYSF Subsystem Flag status bit is set. If the Configuration Register 2 MCOPT1 bit
equals 0, reception of a “transmit vector word” mode command (MC16) causes automatic reset of the
SSYSF status bit in this register; when this occurs, the register bit is reset before status word
transmission begins.
When this bit is asserted, the Terminal Flag status bit is set.
(0x0008)
8
8
7
7
6
6
5
5
4
4
HOLT INTEGRATED CIRCUITS
3
3
MR
2
2
HI-6120, HI-6121
pin Master Reset or SRST software reset. Reads to this register address
1
1
0
0
LSB
18