HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 64

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

CIRCULAR BUFFER MODE 2, Cont.
The host may read the MIBA value to determine the
number of messages that have occurred since
initialization. By reading the initially-zeroed lower bits of
the MIB Address, the host may determine the number of
the next occurring message.
From Table 1, a block of 128 messages requires 8 trailing
zeros in the initial MIBA address, for example, 0x0F00.
After each message is completed, the MIBA value is
updated (0x0F02, 0x0F04, etc.) The device detects
message block completion when all required initially-zero
trailing address bits equal 1 after MIBA is incremented
once. In our example, MIBA would increment from 0x0FFE
to 0x0FFF. When “full count” occurs, the device updates
MIBA to the original value (e.g., 0x0F00) and copies the SA
starting address value to CA current address register,
ready for buffer service by the host. The device optionally
generates a “buffer empty-full” interrupt for the host when
block transfer is completed.
During block transfer, the host can read the MIBA value to
determine the number of additional messages needed
before the N-message data block is complete.
Message processing for all commands begins with the RT
reading the unique descriptor block for the subaddress
specified by the
in the received command word.
For receive subaddresses using Circular Buffer Mode 2,
the device stores received data words in the circular data
buffer. The first data word received for each message is
stored at the location indicated by the CA pointer. After the
correct number of words is received (as specified in the
command word) the device writes Message Information
and Time-Tag words in the Message Information Buffer
then updates the descriptor CA Current Address and MIBA
Message Information pointers for next-message
readiness. If the predetermined total number of messages
has not yet been transacted, MIBA points to the next
location in the message information buffer and CA points to
the next location in the data buffer. If the completed
message is the last message in the block, the CA current
(data) address and MIBA message Information pointers
are reinitialized to their base address values. (Control
Word bits 7:4 tell the device how many MIBA lower bits to
reset.) If the descriptor Control Word IXEQZ bit is asserted
(and if the Interrupt Enable Register IXEQZ bit is asserted)
the device generates a Buffer Full / Empty interrupt,
asserting the
INTMES
T/R
bit, subaddress and word count fields
interrupt output.
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
64
For transmit subaddresses using Circular Buffer Mode 2,
the device transmits data from the assigned RAM buffer,
starting at the location specified by the CA pointer. The first
data word transmitted is stored at the location specified by
the CA pointer. After all data words are transmitted (as
specified in the command word) the device writes
Message Information and Time-Tag words in the Message
Information Buffer then updates the descriptor CA Current
Address and MIBA Message Information pointers for next-
message readiness. If the predetermined total number of
messages has not yet been transacted, MIBA points to the
next location in the message information buffer and CA
points to the next location in the data buffer. If the
completed message is the last message in the block, the
CA current (data) address and MIBA message Information
pointers are reinitialized to their base address values.
(Control Word bits 7:4 tell the device how many MIBA lower
bits to reset.) If the descriptor Control Word IXEQZ bit is
asserted (and if the Interrupt Enable Register IXEQZ bit is
asserted) the device generates a Buffer Full / Empty
interrupt, asserting the
Circular Buffer Mode 2 does not support NOTICE2
segregation of broadcast data, even when the NOTICE2
bit equals 1 in Configuration Register 1. Data words from
broadcast receive commands are stored in the same
buffer with data from non-broadcast receive commands.
The BCAST bit in the Message Information Word reflects
broadcast or non-broadcast status for each stored
message. If broadcast messages to the subaddresss are
not expected during data block transmission or will result in
data block error, the host can illegalize broadcast
commands for the subaddress, either permanently or only
when block transmission is scheduled.
For transmit subaddresses using Circular Buffer Mode 2,
occurrences of broadcast-transmit commands to RT31 do
not result in bus transmission. However these messages
update the Message Information Word addressed by the
Message information Block (MIB) pointer (and the
following Time-Tag Word)
CA pointers remain unchanged
command to the same subaddress, whether broadcast or
not, overwrites the Message Information and Time-Tag
Word locations written by the previous broadcast transmit
command.
INTMES
but afterwards, the MIB and
interrupt output.
. The next transmit