HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 33

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

INTERRUPT LOG BUFFER
Two interrupt output pins notify the host upon occurrence
of pre-determined interrupt-causing events. The interrupt
types are listed below. Each interrupt type only occurs
when the corresponding interrupt type bit is asserted in the
Interrupt Enable Register.
device
control registers, two interrupt output pins and two interrupt
acknowledge input pins. The data sheet section entitled
“Interrupt Management” provides additional details.
Shown in Figure 8, the Interrupt Log Buffer is a 32-word
ring buffer located in shared RAM, at address range
0x0040 to 0x005F.
device interrupt manager maintains information from the
16 most recent interrupts in this buffer. The buffer contains
two information words for each occurring interrupt: the
Interrupt Identification Word and Interrupt Address Word.
The Interrupt Identification Word (IIW) identifies the
occurring interrupt type using a word format identical to the
Pending Interrupt Register. Upon update, all bits except
the occurring interrupt type bit(s) are reset:
IIW - Interrupt Information Word
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
architecture uses an Interrupt Log buffer, three
Interrupt
IXEQZ
IWA
IBRD
——
——
MERR
——
ILCMD
————————————————————
SPIFAIL
LBFA
LBFB
TTINT1
TTINT0
RTAPF
EECKF
RAMIF
To help the host process interrupts, t
Origin
Message
Message
Message
——
——
Message
——
Message
Hardware
Hardware
Hardware
Hardware
Hardware
Hardware
Hardware
Hardware
To manage host interrupts, the
IAW - Interrupt
Address Word
IAW contains the
Command Word
Descriptor Table
Address
IAW contains
0x0000
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
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33
More than one bit may be asserted in an Interrupt
Identification Word. For example, IBR (interrupt broadcast
received) and MERR (interrupt message error) can occur
for the same message. One assertion of the
output pin alerts the host when concurrent message
interrupts occur.
The Interrupt Address Word (IAW) identifies the originating
command for message-based interrupts. When interrupts
originate from message processing, the Interrupt Address
Word (IAW) identifies the interrupt source using the 16-bit
address of the command’s Control Word in the Descriptor
Table. Hardware interrupts are not linked with command
processing. These interrupts write an Interrupt Address
Word value of 0x0000.
After MR reset or SRST software reset, the device
automatically initializes bits 7:0 in the Interrupt Log
Address register to the buffer’s base address, 0x0040. The
bit 7:0 value read will always be even, ranging from 0x0040
to 0x005E. Once terminal operation begins, the current
value of the Interrupt Log Address indicates where the
Interrupt Information Word (IIW) for the next occurring
interrupt will be stored.
On the first interrupt occurring after reset, the device writes
the IIW and IAW to offset locations 00000 and 00001
respectively. The device increments the ring buffer pointer
after each word is stored, storing interrupt information
sequentially in the ring buffer.
sixteenth interrupt are stored in offset locations 0x1E and
0x1F (buffer addresses 0x005E and 0x005F) and the
Interrupt Log Address “rolls over” to again point to offset
location 0 (buffer address 0x0040) where the Interrupt
Information Word for the seventeenth interrupt will be
stored.
Bits 15:8 in the
count of interrupt events since the register was last read.
The interrupt count stops at 255 decimal. Counts greater
than 16 indicate buffer overrun, but the extended count
capacity is provided as a diagnostic aid.
Interrupt Log Address register maintain a
Information words for the
INTMES