HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 70

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

INTERRUPT MANAGEMENT, Cont.
I
Bits 7:0 in this register indicate the IIW storage address
within the buffer for the next occurring interrupt, 0x0040 to
0x005E. Bits 15:8 indicate the number of interrupts since
the register was last read. For further details, see the full
description of the Interrupt Log Address Register.
INTERRUPT ADDRESS WORD (IAW)
Stored in the Interrupt Log Buffer, Interrupt Address Words
(IAW) identify interrupt-causing messages by storing the
descriptor block address for the subaddress or mode code
command that generated each message interrupt.
INTERRUPT IDENTIFICATION WORD (IIW)
Stored in the Interrupt Log Buffer,
Words identify type of interrupt event. Bit assignments
match those used in the Pending Interrupt Register. The
host or subsystem reads the IIW to determine which type of
interrupt occurred. The Interrupt Identification Word is
defined as follows:
RESET AND INITIALIZATION
This section describes the hardware and software reset
mechanisms. Hardware Master Reset returns the device
to the uninitialized state, requiring register/RAM
initialization before terminal execution can begin.
Initialization can be performed by the host after
or automatically, at the user’s option, by reading
configuration data from an external serial EEPROM.
Software reset is asserted by setting the SRST bit in
Configuration Register 1. Software reset has minimal
effect on previously initialized registers and RAM
structures that define terminal behavior. However some
reinitialization may be needed for some applications, after
SRST reset is complete.
MASTER RESET USING THE
AND OPTIONAL AUTO-INITIALIZATION
Hardware master reset is initiated by a low to high
transition on the
up, but may be used anytime afterward. When asserted,
the
hardware reset. Command processing is terminated, the
bus decoders and encoder are cleared, the Time-Tag
count is reset. The Message Error, Busy and Broadcast
Command Received status bits are reset and Terminal
Flag bit is enabled for assertion. All internal logic is cleared.
Registers and RAM structures are restored to the states
shown in Figure 19. The READY, ACTIVE,
INTHW
After
1. After 200ns, the states of the following input pins are
latched into the Operational Status register: RTA4-RTA0,
RTAP, AUTOEN, LOCK and INTSEL. Before READY
NTERRUPT LOG ADDRESS REGISTER
MR
MR
output pins are negated if previously asserted.
pin low to high transition, these steps occur:
input pin causes immediate, unconditional
MR
pin; it should be applied after power-
MR
PIN
Interrupt Identification
HOLT INTEGRATED CIRCUITS
INTMES
MR
HI-6120, HI-6121
reset,
and
70
assertion, a host read cycle to any address returns the
value in the Operational Status register.
2. If the MTSTOFF pin is logic zero, the device performs a
memory test (< 985us). I
bit is set in the BIT Word Register 0x0014. If the MTSTOFF
pin is logic one, the memory test is bypassed. This option
might be chosen if a faster reset process is needed.
Regardless of MTSTOFF state,
address 0x001F are cleared to 0x0000.
3.
checks the latched state of the AUTOEN bit in the
Operational Status register:
If the Operational Status register AUTOEN bit reads
low,
the terminal:
IIW - Interrupt Identification Word
Bit
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
0
After internal processes are initialized, t
A)
state change indicates the host can begin post-
reset initialization of registers and RAM structures.
B) Upon READY assertion, the host should initialize
configuration and option registers, the Descriptor
Table(s) and the Illegalization Table. Initialization may
include data written into the various transmit
subaddress buffers assigned by the initialized
Descriptor Table.
C)
assert the STEX (start execution) bit in Configuration
Register 1 to begin Remote Terminal operation.
auto-initialization is bypassed. The host must initialize
The device asserts the
After the host completes initialization, it must
Interrupt
IXEQZ
IWA
IBRD
——
——
MERR
——
ILCMD
————————————————————
SPIFAIL
LBFA
LBFB
TTINT1
TTINT0
RTAPF
EECKF
RAMIF
Origin
Message
Message
Message
——
——
Message
——
Message
Hardware
Hardware
Hardware
Hardware
Hardware
Hardware
Hardware
Hardware
f memory error occurs,
all RAM locations above
READY
Address Word
IAW contains the
Command Word
Descriptor Table
Address
IAW contains
0x0000
IAW - Interrupt
output pin. This
he device
the BMTF
MR