HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 57

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

INDEXED DATA BUFFERING, Cont.
descriptor block) decrements to zero upon completion of
the message.
single buffer mode. Figure 14 shows a specific example.
To set up a terminal subaddress to buffer multiple
messages, the host writes the desired index count (INDX)
to subaddress descriptor word 3. The initial INDX value
ranges from zero to 3FF hex (1023) messages. The device
decrements the INDX count each time an error-free
message is transacted, and the data pointer is updated to
the first memory address to be used for the next message.
If INDX decrements from one to zero and Control Word
IXEQZ bit 15 is asserted, the IXEQZ bit is set in the
Interrupt Pending Register. If the corresponding bit in the
Interrupt Enable Register is asserted, an
is generated when INDX decrements from one to zero.
INDX counter decrement does not occur if the command
was illegalized or if INDX already equals zero. Once INDX
equals zero, further commands will overwrite the last-
written data buffer block and the data pointer value is not
updated after successful message completion.
When using Index Mode with a non-zero INDX value, the
host must remember the initial Data Pointer A address. The
Data Pointer A word is not automatically reinitialized to the
buffer start address when INDX decrements from 1 to 0.
SINGLE MESSAGE MOD
When Index Mode is initialized with an INDX value of zero,
the subaddress or mode code is operating in “Single
Message Mode”. Here, the same data block is repeatedly
over-read (for transmit data) or overwritten (for receive or
broadcast data). The DPA pointer is not updated at the end
of each message. The chief advantage of single message
mode is simplicity. In comparison to other data buffering
options, the single message buffer uses an absolute
minimum amount of memory space. The IXEQZ interrupt
cannot be used for this scheme (INDX is always zero) but
IWA interrupts may be used. Single message mode is best
suited to synchronous data transfer where the host
processor can reliably read or write new message data
prior to the start of the next message to the same
subaddress or mode code.
BROADCAST MESSAGE HANDLING IN INDEX MODE
For MIL-STD-1553B Notice II compliance, a remote
terminal should be capable of storing data from broadcast
messages separately from non-broadcast message data.
Some applications may not include this requirement. The
standard does not stipulate where data separation should
occur (e.g., within the RT or within the external host) so the
device supports alternative strategies.
When the NOTICE2 bit is logic 1 in Configuration Register
1, broadcast message data is stored in a broadcast data
buffer assigned for the subaddress or mode command.
Each subaddress or mode command must have an
assigned, valid non-zero broadcast buffer address.
Non-broadcast message data is stored in Data Buffer A.
Figure 13 is a general illustration of indexed
E
INTMES
HOLT INTEGRATED CIRCUITS
interrupt
HI-6120, HI-6121
57
There are two ways to deal with broadcast messages in
indexed buffer mode:
Option 1 for Index Mode Broadcast Messages:
The first alternative isolates broadcast message
information in the broadcast data buffer. If the descriptor
Control Word IBRD bit and Interrupt Enable Register IBRD
bit are both set, reception of broadcast messages
generates an
data buffer must be processed before another broadcast
message arrives to prevent loss of data. Broadcast
messages do not decrement the INDX register, and Data
Pointer A is not updated in message post-processing. This
scheme may be well suited for Single Message Mode
(INDX = 0) when the host can reliably service either the
broadcast data buffer or data buffer A before the next
receive message arrives for the same subaddress (or
mode code).
Option 1 Setup:
in Configuration Register 1 and sets the Control Word
IBRD (Interrupt Broadcast Received) bit for each index
mode descriptor block. The IBRD bit is also asserted in the
Interrupt Enable Register.
When a broadcast command is received, message
information and data are stored in the broadcast data
buffer. If descriptor Control Word IBRD bit is set, an
INTMES
Interrupt Log to determine the originating subaddress (or
mode code) then service the broadcast data buffer for that
subaddress (or mode code) before the next broadcast
message to the same subaddress (or mode code) arrives.
Option 2 for Index Mode Broadcast Messages:
The second alternative stores both broadcast and non-
broadcast message information in data buffer A. Optional
IBRD interrupts can signal arrival of broadcast messages.
The RT handles broadcast messages just like non-
broadcast messages, except the Message Information
Word BCAST bit is asserted to identify broadcast
messages during host buffer servicing. All messages
decrement the INDX register and Data Pointer A is updated
in message post-processing. This scheme is compatible
with Single Message Mode or conventional N-message
indexing. For Notice II compliance, separation of
broadcast and non-broadcast data occurs within the host.
Option 2 Setup:
NOTICE2 bit in Configuration Register 1. If broadcast
interrupts are used, the Control Word IBRD (Interrupt
Broadcast Received) bit is asserted at each desired index
mode descriptor block . The IBRD bit is also asserted in the
Interrupt Enable Register.
Using option 2, the host has several options for servicing
data buffer A: (a) when INDX decrements from one to zero
(using the IXEQZ interrupt), (b) when a broadcast
message occurs (using the IBRD interrupt) or (c) when any
message arrives (using the IWA interrupt).
interrupt is generated. The host must read the
INTMES
At initialization, host asserts NOTICE2 bit
At initialization, host negates the
interrupt to the host. The broadcast