HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 69

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

INTERRUPT MANAGEMENT
HOST MESSAGE DETECTION OPTIONS
Upon receiving messages, the host has several options.
The individual descriptor table Control Words have enable
flags for generating interrupts. Interrupts can be enabled
on a subaddress or mode code basis. For any subaddress,
interrupts can be enabled for (a) every command
occurrence, (b) upon occurrence of broadcast commands,
(c) at end of multiple message block transfers (index mode
or circular buffer modes only), or (d) no interrupts at all.
Some subaddress commands may not require immediate
host servicing. If the number of legal subaddresses is
small, the host can poll descriptor table Control Words for
the legal subaddresses to detect message activity. The
Control Word’s DBAC bit (descriptor block accessed) is set
whenever a message is processed. This bit is
automatically reset by any host read cycle to the descriptor
Control Word. Whenever the DBAC bit reads high, the
subaddress transacted a message since the last Control
Word read cycle.
Another interrupt alternative that works for any number of
legal subaddresses (or when illegal command detection is
not used) is to poll the device ACTIVE pin. This pin is high
whenever a command is being processed. After the
ACTIVE pin goes low, the host can read the Current
Command Register to determine the processed command
word, or may fetch the command's descriptor table
address from the Current Control Word Address register.
Both registers maintain their loaded values until the next
valid command to the terminal is decoded.
HOST INTERRUPT GENERATION
Interrupts are output signals notifying the host when
predetermined events have occurred during terminal
operation; the interrupt-causing events are fully
programmable. The host defines message-specific
interrupt-causing events when initializing the Descriptor
Table. Other hardware-based interrupts are configured
when internal device registers are initialized.
To manage host interrupts, the device architecture
involves an Interrupt Log buffer, three control registers, two
interrupt output pins and two interrupt acknowledge input
pins. The three internal registers are the Pending Interrupt
Register, the Interrupt Enable Register and the Interrupt
Log Address Register. The Pending Interrupt Register
contains information identifying events programmed by
the host to generate interrupts. The Interrupt Enable
register lets the host enable or disable interrupt generation
for different interrupt-causing events. The Interrupt Log
Buffer is a 32-word ring buffer located in shared RAM
address range 0x0040 to 0x005F.
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
69
Separate interrupt outputs are provided for hardware
interrupts (
The host programs both pins as either pulsed interrupt
outputs or level-sensitive outputs, by writing t
in Configuration Register 1:
Register 1
Pulsed outputs have brief (~250ns) duration, sufficient to
drive edge-triggered host inputs. In the level mode of
operation, asserted interrupts remain low until
acknowledged by the host. There are two ways the host
can acknowledge level interrupts: (1) assert the ACKHW or
ACKMES input pin to clear the respective interrupt
or
Register to clear both
the high state.
Assertion of the
causing hardware event that is enabled in the Interrupt
Enable Register. D
listed in the table on the following page. When the
output is asserted, one or more bits are set in the
Interrupt Register, to identify the interrrupt event(s).
Assertion of the
completed indicates a predetermined message event
occurred
Register and (2) specifically enabled for the last command
transacted
command is programmed by the host to enable events that
generate message interrupts. The type of
reflected in the IXEQZ, IWA, IBR, ILCMD and MERR bits
within the Pending Interrupt Register.
The interrupt architecture maintains information for the last
16 interrupts in a 32-word ring buffer. The device
automatically handles interrupt-logging overhead. Each
interrupt generates two words of information to help the
host perform interrupt processing. The Interrupt
Identification Word (IIW) identifies the type(s) of interrupt
that occurred. The Interrupt Address Word (IAW) identifies
the interrupt source (e.g., subaddress Descriptor Block)
using a 16-bit address.
Config.
INTSEL
INTMES
Bit
0
1
that is (1) globally enabled in the Interrupt Enable
. The Descriptor Table Control Word for each
INTHW
output, or (2) read the Pending Interrupt
Pulse Output
Level Output
Active Low
Active Low
INTHW
Interrupt
INTMES
INTMES
) and message interrupts (
Output
INTHW
Pins
efined
INTHW
interrupt indicates an
interrupt after a message is
interrupt-causing events are
and
INTMES
(internal pull-downs)
Acknowledge
The ACK pins
are not used.
Active High
Input Pins
INTMES
Interrupt
ACKMES
ACKHW
he INTSEL bit
output pins to
INTMES
interrupt-
Pending
event is
INTHW
INTHW
).