HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 24

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

REGISTERS, Cont.
ALTERNATE BUILT-IN TEST WORD REGISTER
This 16-bit register is Read-Write and is fully maintained by the external host. This register is cleared after
but unaffected by SRST software reset.
If the ALTBITW option bit in Configuration Register 2 equals one when a valid “transmit BIT word” mode command (MC19) is
received, the current value in this register is transmitted as the mode data word in the terminal response. The value is also
copied to the assigned data buffer for MC19, after mode command fulfillment.
RESERVED REGISTER
Register 0x0016 is used for factory testing. It is cleared after
TEST input pin is low.
TEST CONTROL REGISTER
This register controls RAM built-in self-test, and transceiver loopback testing. Bits 3-4 and 8-9 are Read Only. The remaining
bits in this register are Read-Write but can be written only when the TEST input pin is high. This register is cleared after
master reset, or SRST software reset. This register supports two types of test: Register bits 15 - 8 are used for RAM built-in self
test (RAM BIST). Register bits 7 -2 are used for transceiver loopback testing (either digital loopback or analog loopback).
Under internal logic control, this device uses one RAM self test (Inc / Dec Test described below) to check internal RAM memory
after
Register bits 13:11 select RAM test type. Then bit 10 starts the selected RAM test, and bits 9-8 report a pass/fail result after test
completion. All tests are destructive, overwriting data present before test commencement.
Bit No.
15
14
13-11
MSB
MSB
MR
15 14 13 12 11 10 9
15 14 13 12 11 10 9
15 14 13 12 11 10 9
pin master reset. Test Control Register bits 15 - 8 provide a means for the host to perform RAM self-test at other times.
ALTERNATE BUILT-IN TEST WORD REGISTER 15:0
FRAMA
RBFFAIL
RBSEL2-0 RAM BIST Select Bits 2-0.
Mnemonic Interrupt Type
Full RAM Access Enable.
RAM BIST Force Failure.
During normal operation, some bits in certain RAM locations (e.g., Descriptor Table Control Words)
cannot be written by the host. When the FRAMA bit is asserted, host writes to RAM are unrestricted
to permit full testing. During normal completion, this bit must be reset to logic 0.
When this bit is asserted, RAM test failure is forced to verify that RAM BIST logic is functional.
This 3-bit field selects the RAM BIST test mode applied when the RBSTART bit is set:
RBSEL2:0
000
001
010
011
100
101
110
111
8
8
8
(0x0016)
0
7
7
7
0
6
6
6
(0x0017)
SELECTED RAM TEST
5
5
5
Idle
Pattern Test, described below . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.42ms
Write 0x0000 to RAM address range 0x0000 - 0x7FFF . . . . . . . . . . . . 170us
Read and verify 0x0000 over RAM address range 0x0000 - 0x7FFF . . . 500us
Write 0xFFFF to RAM address range 0x0000 - 0x7FFF . . . . . . . . . . . . 170us
Read and verify 0xFFFF over RAM address range 0x0000 - 0x7FFF . . 500us
Inc / Dec Test performs only steps 5 - 8 of the Pattern Test below . . . . . . 1.32ms
Idle
4
4
4
HOLT INTEGRATED CIRCUITS
3
3
3
2
2
2
HI-6120, HI-6121
1
1
1
0
0
0
LSB
LSB
24
MR
(0x0015)
pin master reset and cannot be written by the host while the
MR
pin master reset
TEST TIME
MR
pin