HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 7

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

FUNCTIONAL OVERVIEW, Cont.
MEMORY AND REGISTER ADDRESSING
Interrupt Log
The device maintains information from the last 16 interrupts
in a 32-word circular buffer in shared RAM known as the
Interrupt Log. Two 16-bit words characterize each interrupt;
one word identifies the interrupt type (Interrupt Identification
Word) and one word identifies the command that generated
the interrupt (Interrupt Address Word). After reset, the
Interrupt Log Address Register is reset to the fixed starting
address of the 32 word Interrupt Log. After each occurring
interrupt, the device updates the register to point to the log
address used for the next occurring interrupt.
HARDWARE FEATURE SUMMARY
Clock Inputs
A 50 MHz master clock input is required. The Time-Tag
counter clock is selected from six internally generated
frequencies, or may use an external clock input signal.
Remote Terminal Address Inputs
The 5-bit Remote Terminal address is set using pins RTA0 to
RTA 4. The RTAP input pin should be set or reset to present
matching odd parity. The state of the RT address and parity
pins is latched into the Operational Status register upon
rising edge on the
LOCK input is latched into the Operational Status register at
the same time, and controls whether or not the active
terminal address and parity in the Operational Status
register can be overwritten by host writes into the register.
Between Master Reset assertions, the state of the RTA and
RTAP inputs is “don’t care”. If the value of RT address and
parity in the Operational Status register has parity error,
terminal operation is disallowed.
Integral Time-Tag Counter
A free-running 16-bit counter provides time-tag values that
are recorded for each message transacted. The time-tag
The HI-6120 and HI-6121 have an internal address space of
32K 16-bit words. All memory addresses in this data sheet
are expressed as hexadecimal numbers, using the C
programming convention where the prefix “0x” denotes a
hexadecimal value; e.g., 0x00FF represents 00FF hex.
All device RAM and register address mapping is word
oriented, rather than byte oriented. Register and memory
addresses throughout this document reflect word
addressing. For all HI-6121 and most HI-6120 applications,
word oriented addressing applies. W
addressing with the HI-6120 uses address inputs A15 to A1;
address input A0 is not used as fifteen bits are sufficient for a
32K address range.
MR
master reset input. The state of the
HOLT INTEGRATED CIRCUITS
ord oriented
HI-6120, HI-6121
7
counter can be clocked from one of six internally generated
frequencies, or from an external source. The user can
enable automatic counter synchronization in response to
“synchronize” mode commands, and optional host interrupts
are provided for time-tag counter roll-over, and counter
match to a stored value in the Time-Tag Utility register.
Dual Bus Transceivers
Built-in bus transceivers provide direct interface between
the device and MIL-STD-1553 bus isolation transformers.
The transceivers convert digital data to and from differential
Manchester II encoded bus signals. A pair of “transmit
inhibit” input pins exercises direct control over transmission
for both buses.
The RT contains separate Manchester II encoders and
decoders for each bus. Encoder-decoder logic interfaces
directly with the dual-bus MIL-STD-1553 transceivers. The
decoder checks for proper sync pulse and Manchester
waveform, edge skew, correct number of bits and parity.
During transmission, each encoded word is looped back
through the decoder to check for errors. Bus sampling is
clocked at 25 MHz, providing superior tolerance to zero-
crossing distortion.
Auto-Initialization Serial EEPROM Interface
The device has an automatic self-initialization feature. If self-
initialization is enabled after
reads configuration settings from external serial EEPROM
to load the Descriptor Table, Illegalization Table, transmit
mode command data and registers for terminal operation.
Self-initialization can optionally initialize transmit data
buffers with fixed data from EEPROM. A mechanism is
provided to initially program or later modify the external
serial EEPROM memory, by copying host-loaded tables and
register values to the serial EEPROM.
HI-6120 ONLY:
bus interface HI-6120 is able to use byte transfers.
microprocessors (and some 16-bit and 32-bit
microprocessors) use (or can use) byte-oriented memory
accesses.
sixteenth bus address input, A0. Byte oriented addressing
with the HI-6120 uses all 16 address pins, A15 to A0 to
address 64K bytes. The A0 input denotes whether the first or
second byte in the word is being addressed, while A15-A1
indicate the word address. This difference must be
considered when assigning HI-6120 pointer values or
accessing RAM or registers. From the microprocessor’s
standpoint, any host-assigned RAM buffer address will be
double the value of the buffer’s pointer stored in RAM.
paragraph only applies to HI-6120 using 8-bit bus width.
Encoder and Decoders
To provide byte capability, the HI-6120 has a
When required by the application, the host
MR
master reset, the device
All 8-bit
This