HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 4

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

PIN DESCRIPTION, Cont.
THESE PINS APPLY TO BOTH HI-6120 AND HI-6121
* Note: These pins are combined into the ACKINT pin on HI-6121PQx variant.
BUSA,
BUSB,
VCC, VCCP
ACKMES*
ACKHW*
TEST7:0
B
MODE
COMP
ESCK
MISO
MOSI
TEST
PIN
GND
ENDI
CE
BUSA
BUSB
ANALOG
ANALOG
OUTPUT
OUTPUT
POWER
POWER
TYPE
INPUT
INPUT
BI-DIR
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Serial Clock output signal for the dedicated auto-initialization SPI connected to external
auto-initialization EEPROM.
Serial Input signal (Master-In Slave-Out) for the dedicated auto-initialization SPI
connected to external auto-initialization EEPROM.
Serial Output signal (Master-Out Slave-In) for the dedicated auto-initialization SPI
connected to external auto-initialization EEPROM.
Bi-directional analog interface to MIL-STD-1553 bus A isolation transformer, positive and
negative signals respectively.
Bi-directional analog interface to MIL-STD-1553 bus B isolation transformer, positive and
negative signals respectively.
3.3V supply voltage inputs for logic and transceiver circuits
Ground pin for logic and transceiver circuits
Test enable.
self-test or loopback tests.
Test pins used for factory testing.
these pins.
Test pin used for factory testing.
Test pin used for factory testing.
pin.
Chip Enable, active low. Internal 50K
host read or write accesses to device RAM or registers. On HI-6121, it is normally
connected to a host SPI chip select output signal.
Configuration pin for selecting “endianness” of the host bus interface when byte transfers
are used. Internal 50K
indicates whether integers are represented with the most significant byte stored at the
lowest address (big endian) or at the highest address (little endian). Internal storage is
“big endian.” When using the HI-6120, this pin only applies when the host bus is
configured for 8-bit width, that is, when BWID equals 0. When the HI-6120 is configured
for 16-bit bus width, the BENDI input pin is “don’t care.” When using the HI-6121, this
pin controls the byte order of the 16-bit data following the SPI command.
When BENDI is low, “little endian” is chosen; the low order byte (bits 7:0) is transacted
before the high order byte (bits 15:8). When BENDI is high, “big endian” is chosen and
the high order byte is transacted on the host bus before the low order byte.
Hardware Interrupt Acknowledge, active high.
input is
level interrupts. After interrupt assertion causes the
state (60ns minimum duration) on ACKHW will clear the
interrupt is also cleared by reading the Pending Interrupt Register.
Message Interrupt Acknowledge, active high.
is
interrupts. After interrupt assertion causes the
(60ns minimum duration) on ACKMES will clear the
interrupt is also cleared by reading the Pending Interrupt Register.
only used when the INTSEL bit in Configuration Register 1 is asserted to enable level
only used when the INTSEL bit in Configuration Register 1 is asserted to enable
HOLT INTEGRATED CIRCUITS
Internal 50K
HI-6120, HI-6121
W
pull-up resistor. Endianness is the system attribute that
W
4
pull-down resistor.
Internal 50K
Internal 50K
Internal 50K
DESCRIPTION
W
pull-up resistor. When asserted, this pin enables
W
W
Internal 50K
Internal 50K
W
INTMES
The host asserts this pin to perform RAM
pull-up resistor.
pull-down resistor.
pull-down resistor.
Internal 50K
INTMES
INTHW
output to go low, a high state
INTHW
W
W
pull-down resistor. This input
pull-down resistor. This
output to go low, a high
output to logic 1. The
W
output to logic 1. The
Do not connect this pin.
pull-down resistor.
Do not connect this
Do not connect