HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 62

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

CIRCULAR BUFFER MODE 2
CIRCULAR BUFFER MODE 2
Circular Buffer Mode 2 segregates message data and
message information in separate host-defined buffers.
Separating data from message information simplifies the
host software that loads or unloads the data to or from the
buffer. After a predetermined number of messages has
been transacted, buffer address pointers for data and
message information are automatically reset to their base
addresses. Figure 17 is a generalized illustration of
Circular Buffer Mode 2, while Figure 18 shows a specific
example.
Circular Buffer Mode 2 is selected when the Control Word
PPEN bit is zero and the CIR2EN bit is logic 1. When the
CIR2EN bit is high, the CIR1EN bit is don't care. The
descriptor Control Word DPB bit is not used.
Any receive subaddress using circular buffer mode 2 has
two circular buffers: a data storage buffer and a message
information buffer. A separate buffer pair may be used for
transmit commands to the same subaddress, if it also uses
circular buffer mode 2. Each transmit and receive
subaddress using circular buffer mode 2 may have unique
data buffer and message info buffer assignments. Careful
management (involving the bus controller) may allow
buffer sharing, as long as multiple message sequences to
a given subaddress are not interrupted by messages to
other subaddresses that use the same buffer space.
When a subaddress uses circular buffer mode 2, its
Descriptor Table 4-word block is defined as follows:
If Descriptor Word 1 is stored at memory address N,
Descriptor Word 2 is stored at address N+1, and the other
two words are stored at addresses N+2 and N+3. The first
Descriptor Word 1
Descriptor Word 2
Descriptor Word 3
Descriptor Word 4
—————
Messages
Number
128
256
512
16
32
64
of
2
4
8
Control Word
SA
CA
MIBA Message Info Buffer addr
———————
CIR2ZN Field
Control Word
Buffer start address
Buffer current address
1010 (A)
0010 (2)
0100 (4)
0101 (5)
1000 (8)
1001 (9)
0011 (3)
0110 (6)
0111 (7)
Bits 7:4
Initialization Factors Based on Message Block Size
HOLT INTEGRATED CIRCUITS
Table 1. Circular Buffer Mode 2
HI-6120, HI-6121
———————
32 Words / Msg
Data Space, if
Required
16,384
1,024
2,048
4,096
8,192
128
256
512
64
62
word in the descriptor block is the Control Word. The
second and third words in the descriptor are the Start
Address (SA) and Current Address (CA) pointers. The
Message Information Buffer Address (MIBA) points to the
storage location for the Message Information Word from
the next occurring message.
Each time a message is completed, the device writes a
new Message Information Word and Time-Tag Word in the
MIB (Message Information Buffer) at the MIBA address
and following location, respectively. The MIBA pointer is
not updated if message error occurred, if the Busy status
bit was set, or if the command was illegalized (for example
an illegal word count expressed in the command word.)
For these situations, the Message Information and Time-
Tag words are still written, but MIB updates for the
following message will overwrite the just-written Message
Information and Time-Tag word addresses.
For error-free receive messages, received data words are
stored in the data buffer after message completion,
starting at the CA address value. The CA value is then
updated for next-message readiness.
After writing the two MIB words, the device updates the
MIBA value to show the buffer address to be used by the
next message. Until the predetermined number of error-
free messages is transacted, the MIBA value is double-
incremented at each update. Before updating the MIBA in
Descriptor Word 4, the pre-existing MIBA value is
incremented once then checked for ‘full count,” occurring
when all N low-order address bits initialized to zero
(explained below) become N “one” bits. Full count means
the predetermined number of successful messages was
completed. When this occurs, the CA and MIB pointers are
automatically written to their initialized values by the
device.
To preserve data integrity, the TRXDB bit should be set in
Control Register 2 to avoid storing incomplete data from
———————
2 Words / Msg
MIB Space,
Required
1,024
128
256
512
16
32
64
4
8
Leading & Trailing Zeros
——————————
Showing the Required
0
0
0
0
0
0
0
0
0
xxxxxxxxxxxx00
xxxxxxxxxxx000
xxxxxxxxxx0000
xxxxxxxxx00000
xxxxxxxx000000
xxxxxxx0000000
xxxxxx00000000
xxxxx000000000
xxxx0000000000
Initial MIBA Value,
(14 address bits)