HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 44

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

DESCRIPTOR TABLE, Cont.
13
12
11
10
9
8
IBRD
MKBUSY
DBAC
DPB
BCAST
PPON
interrupts are enabled, an IWA interrupt is entered in the Pending Interrupt Register, the
output pin is asserted, and the interrupt is registered in the Interrupt Log.
Interrupt Broadcast Received.
If the Interrupt Enable Register IBRD bit is high, assertion of this bit enables interrupt generation at
each instance of a valid broadcast transmit mode code command. Upon completion of command
processing, when IBRD interrupts are enabled, an IBRD interrupt is entered in the Pending Interrupt
Register, the
bit has no function if the BCSTINV bit is high in Configuration Register 1. In this case, commands to
RT address 31 are not recognized as valid by the device.
Make Busy.
The host asserts the MKBUSY bit to respond with Busy status for commands to this mode code. This
bit is an alternative to globally applying Busy status for all valid commands, enabled from the 1553
Status Bits Register. See that register description for additional information. When Busy is asserted,
mode data words are not transmitted with MC16-MC31, and the DPB bit does not toggle after
message completion. The MKBUSY bit is not heeded if set in the Control Word for mode code
command MC8 “reset remote terminal”. For this command only, Busy is inhibited for the status
response transmitted before the reset process begins.
Descriptor Block Accessed.
Internal device logic asserts the DBAC bit upon completion of message processing. The host may
poll this bit to detect mode command activity, instead of using host interrupts. This bit is reset to logic 0
by
Data Pointer B.
This status bit is maintained by the device and only applies for mode commands using ping-pong
buffer mode. This bit indicates the buffer to be used for the next occurring mode command. When the
DPB bit is logic 0, the next message will use Data Pointer A; when DPB is logic 1, the next message
uses Data Pointer B. In ping-pong buffer mode, the bit is inverted after each
completion. The DPB bit is not altered after messages ending in error, after illegal commands, or after
messages when the terminal responds with Busy status. This bit is reset to logic 0 by
or SRST software reset; therefore the first message received after either reset will use Buffer A. This
bit is “don’t care” for indexed single-buffer mode.
Broadcast Received.
Device logic sets this bit when a valid broadcast mode command is received having
bit has no function if the BCSTINV bit is asserted in Configuration Register 1. In this case, RT address
31 commands are not recognized as valid by the HI-6120. This bit is reset to logic 0 by
reset or SRST software reset.
Ping-Pong Enable Acknowledge.
This bit is read only and only applies for mode commands using ping-pong mode (PPEN bit 2 was
initialized to logic 1 by the host after reset). The device asserts this bit when it recognizes ping-pong is
active for this mode code. Before loading the transmit data buffer for this mode code, the host can ask
the device to temporarily disable ping-pong by asserting STOPP bit 3. The device acknowledges
ping-pong is disabled by negating PPON. The host can safely load or off-load the buffer without data
collision while PPON is negated. After buffer servicing, the host asks the device to re-enable ping-
pong by negating STOPP bit 3. The device acknowledges ping-pong is re-enabled by asserting
PPON.
If PPEN bit 2 is asserted and PPON bit 8 is negated when a new command arrives for this mode code,
ping-pong disable handshake is in effect: The device applies single-buffer index mode using Data
Pointer A or Data Pointer B, per DPB bit 10. The DPB bit does not toggle after command completion.
MR
master reset, SRST software reset or a host read cycle to this memory address.
INTMES
HOLT INTEGRATED CIRCUITS
output pin is asserted, and the interrupt is registered in the Interrupt Log. This
HI-6120, HI-6121
44
error-free
MR
T/R
master reset
bit = 1. This
MR
message
INTMES
master