HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 5

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

PIN DESCRIPTION, Cont.
THESE PINS APPLY TO HI-6120 ONLY
THESE PINS APPLY TO HI-6121 ONLY
.
WAIT or
(HI-6121PQx
variant only)
STR
R/
A15:1 and
ACKINT
A0 (
BTYPE
WPOL
D15:0
W
BWID
PIN
PIN
SCK
SO
SI
or
or
LB
WAIT
WE
OE
)
OUTPUT
OUTPUT
INPUTS
TYPE
TYPE
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I/O
Tristate data bus for host read/write operations upon registers and shared RAM.
Internal 50K
bus width can be configured for 8 or 16 bits. For 8 bit bus width, pins D15:8 are not
connected; each 16-bit word is transacted as a pair of upper and lower byte operations,
with data presented sequentially on pins D7:0. For compatibility with different host
processors, when byte transfers are enabled the BENDI input pin sets whether the low
order byte is transferred before the high order byte, or vice versa.
Address bus for host read/write operations upon registers and shared RAM. For 16-bit
bus width, address bit A0 (
equals 0 during the first byte read/write access; while A0 equals 1 during the second
byte access.
Configuration pin for host bus width.
bus width, low selects 8-bit bus width.
Configuration pin for host bus read/write control signal style. Internal 50K
resistor. High selects “Intel style” using separate read strobe
write strobe
read/write select signal, R/ .
R/
is high. Internal 50K
RAM or registers. Important: This pin or the
transitions.
Common
BTYPE pin is high. Internal 50K
to device RAM or registers.
Host bus read cycle “wait” output. For
output can be made active high or active low, set by the state of the WPOL input pin.
The WAIT output may be ignored when the host processor’s read cycle time is
sufficiently slow to meet worst case (slowest) read cycle timing for this device, or when
wait cycles have been enabled from the processor. The WAIT output is useful when the
host processor runs at high clock rates and/or when processor read wait states do not
provide adequate timing margin for worst case (slowest) read cycle timing for this
device.
Configuration pin for WAIT output polarity.
is low, the “wait” output is active low (
active high (WAIT). A multiple word sequential read will always assert WAIT during the
first read cycle. As long as successive reads are sequential, no further wait output
occurs.
Serial Peripheral Interface (SPI) Serial Output pin. SO is normally connected to MISO
(Master In - Slave Out) pin on host SPI port. The SO pin is tri-stated when not
transmitting serial data to host.
Serial Peripheral Interface (SPI) Serial Input pin.
normally connected to MOSI
(Master Out - Slave In) pin on host SPI port.
Serial Peripheral Interface (SPI) Serial Clock pin.
SCK is normally connected to SCK output pin on host SPI port
Interrupt Acknowledge, active high.
used when the INTSEL bit in Configuration Register 1 is asserted to enable level
interrupts. After interrupt assertion causes the
high state (60ns minimum duration) on ACKINT will clear the
to logic 1. Interrupt are also cleared by reading the Pending Interrupt Register.
W
(read/write) signal when BTYPE pin is low, or
HOLT INTEGRATED CIRCUITS
STR
W
WE
pull-down resistors.
(
HI-6120, HI-6121
read/write s
. Low selects “Motorola style” using single read/write strobe
W
pull-up resistor. Used for host read or write accesses to device
LB
W
trobe) when BTYPE pin is low, or
5
) from the host is not used. For 8-bit bus width, bit A0
W
pull-up resistor. Used for host read or write accesses
All read/write operations transact 16 bit words, but
DESCRIPTION
DESCRIPTION
Internal 50K
Internal 50K
WAIT
compatibility with different host processors, this
Internal 50K
). When WPOL is high, the “wait” output is
CE
INTHW
W
pin should be high during all address
W
Internal 50K
Internal 50K
pull-down resistor. This input is
WE
pull-up resistor. High selects 16-bit
W
(write enable) when BTYPE pin
or
pull-up resistor. When WPOL
INTMES
OE
INTHW
OE
W
W
pull-down resistor.
pull-down resistor.
(output enable) when
(output enable) and
output to go low, a
or
INTMES
W
pull-up
STR
output
and
only
SI is