HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 72

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

RESET AND INITIALIZATION, Cont.
If the Operational Status register AUTOEN bit reads
high
EEPROM via the dedicated EEPROM SPI port:
The
self-initialization proceeds. The device reads
initialization data from the external serial EEPROM
memory, using the dedicated EEPROM SPI port.
Initialization includes
secondary Descriptor Tables, if used) and can include
initial data written to transmit subaddress data buffers
allocated by the Descriptor Table.
During auto-initialization, the written value for each
register or RAM location is read back for confirmation.
If the read-back value does not match the
corresponding value from EEPROM, an initialization
error is saved. This error results in action (described
below) that occurs when the initialization process is
finished.
W
tallied as follows, using EEPROM data read from the
1K or 32K address range. A properly configured serial
EEPROM contains a 16-bit checksum value stored at
the pair of EEPROM locations corresponding to RAM
address 0x0020. The stored checksum is tallied as if
RAM address 0x0020 equals 0x0000 and five
registers are excluded from checksum computation:
Operational Status register 0x0002, Pending Interrupt
register 0x0006, Time-Tag register 0x0008 and BIT
Word register 0x0014. The stored value is actually the
twos-complement of the 16-bit memory checksum,
(
During initialization, byte pairs are sequentially read
from EEPROM, then merged to a 16-bit value that is
both written to device RAM (or register) and added
(running tally) to the twos-complemented checksum
value. When the full 1K or 32K EEPROM range is
tallied, the running checksum tally should equal zero,
indicating error-free checksum tally. After initialization
(at READY assertion), the 16-bit twos-complement
checksum value is copied from EEPROM to device
RAM address 0x0020. This is part of the Temporary
Receive Data Buffer, which does not interfere with
terminal initialization.
, the device initializes itself from an external serial
CHECKSUM
hile performing initialization, a running checksum is
If the EE1K pin is low,
32K address range 0x0 to 0x7FFF, including the
entire RAM. Therefore it can initialize secondary
Descriptor Tables and transmit subaddress
buffers in the upper RAM space.
If the EE1K pin is high,
the 1K address range 0x0 to 0x003F. This covers
all registers and the minimum set of required
tables, including the primary Descriptor Table from
0x00200 to 0x003FF. F
is the only Descriptor Table.
READY
output pin remains low while automatic
+ 1).
all registers, all tables (including
initialization covers the full
or many applications,
initialization covers just
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
this
72
A method for programming the EEPROM itself from a fully
configured terminal is explained in a following section
entitled “
When the device completes auto-initialization, the
READY
If an initialization error occurred, these events take
place immediately after READY assertion: (1) the
INTHW
Operational Status Register 0x0002 is written to
indicate the type of error. The EECKF or RAMIF bit is
set to show checksum failure or read-back data
mismatch between RAM and EEPROM.
EELF bit is set in the Built-In Test Word Register
0x0014. (4) If RAMIF read-back error occurred, the
address of the first occurring instance is written to
register address 0x001F. Additional locations beyond
the saved address may have mismatch, but only the
first instance is logged.
The STEX bit in Configuration Register 1 is still zero.
If the STEX bit in the initialization EEPROM is high
and if the EECKF, RAMIF and RTAPF bits are reset in
the Operational Status Register 0x0002, t
now sets the STEX bit to start Remote Terminal
operation
error-free and (2) the RT address in Operational
Status Register bits 15-10 has correct parity. The
register’s terminal address bits reflect input pin states
if the LOCK pin is high, or were overwritten by values
from the initialization EEPROM, if the LOCK pin is low.
If automatic STEX assertion was blocked because
EECKF or RAMIF bits were written high after READY
assertion, the host can write STEX high, overriding the
error condition. If STEX assertion was blocked
because of RT address parity error, the STEX bit
cannot be asserted until the parity error is corrected.
The host may overwrite the Operational Status
Register RTAP4-0 and RTAP bits to correct the error,
then assert the STEX bit in Configuration Register 1.
If the STEX bit in the initialization EEPROM is low,
the STEX bit in
asserted at this time. The device awaits STEX
assertion by a host write to Configuration Register 1
before starting Remote Terminal operation. The STEX
bit may be written any time after the
goes high.
After any
pins (
RTA4 to RTA0 and RTAP) are latched into Operational
Status Register 0x0002. Because
follows master reset,
overwritten by the values stored in the initialization
EEPROM bytes corresponding to register address
0x0002, only if the LOCK input pin is low.
Serial EEPROM Programming Utility
AUTOEN, LOCK and terminal address pins
output pin is asserted to the high state.
interrupt output pin is asserted. (2) the
. This means: (1)
MR
master reset, the state of certain input
Configuration Register 1 is not
the mirrored pin states may be
auto-
READY
initialization was
auto-initialization
he device
output pin
(3) The
”. If a
,