HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 3

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

PIN DESCRIPTION
THESE PINS APPLY TO BOTH HI-6120 AND HI-6121
MTSTOFF
EECOPY
AUTOEN
INTMES
TXINHA
TXINHB
ACTIVE
READY
INTHW
RTA4:0
SSYSF
TTCLK
MCLK
LOCK
EE1K
RTAP
PIN
ECS
MR
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUTS
INPUTS
TYPE
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Hardware Interrupt output, active low.
pulse output or as a level output by the INTSEL bit in Configuration Register 1.
Message Interrupt output, active low. This signal is programmed as a brief low-going
pulse
Master Reset, active low.
software reset by asserting the SRST bit in Configuration Register 1.
Memory test disable, active high.
the device performs a memory test on the entire RAM after rising edge on the
pin. When this pin is high, the RAM test is skipped, resulting in a faster reset process.
For further information, r
EEPROM Copy, active high.
the process that copies registers and configuration tables to serial EEPROM. Refer to
the data sheet section entitled “Reset and Initialization.”
Auto-Initialize Enable
rising edge on
data to registers and RAM from an external serial EEPROM
initialization SPl port.
When the AUTOEN pin is high, the EE1K input sets the range of the auto-initialization
process. When EE1K is low, registers and RAM occupying the 32K address range from
0x0 to 0x7FFF are initialized. For applications needing faster initialization, when EE1K is
high, only registers and RAM occupying the 1K address range from 0x0 to 0x03FF are
initialized. This pin has an i
this pin is not used.
Remote terminal address bits 4 - 0, and parity bit.
RTAP pin should provide odd parity for the address
address and parity pin levels are latched into the Operational Status register when rising
edge occurs on the
reflects the active terminal address. The register value can be overwritten by the host
under some circumstances. See
Internal 50K
LOCK bit when rising edge occurs on the
bit is high, terminal address in the register cannot be overwritten by a host register write.
If Operational Status register LOCK bit is low, the host can overwrite the five terminal
address bits and address parity bit in the Operational Status register.
Transmit Inhibits for Bus A and Bus B, active high.
These inputs are logically ORed with the corresponding TXINHA and TXINHB bits in
Configuration Register 1. If the input pin or register bit is high, bus transmit is disabled.
Pin is low when auto-initialization or built-in test is in-process. Host should not access
shared RAM or device registers when pin state is low. When output is high, the shared
RAM and registers may be configured, and device will begin terminal execution when
the STEX (start execution) bit in Configuration Register 1 is set.
Pin is high when the HI-6120 is actively processing a 1553 command, otherwise low.
Master clock input, 50.0 MHZ ±0.01% (100ppm).
Time-Tag Clock input.
bits TTCK2:0 = 001, this pin is the clock input for the Time Tag counter. For other values
of TTCK2:0, the Time-Tag counter is internally clocked so the TTCLK pin is not used.
Subsystem fail input, active high.
high, the HI-6120 terminal sets the SUBSYS flag in its status word.
Chip select output for the dedicated Serial Peripheral Interface (SPI) that connects to
the optional external serial EEPROM used for automatic self-initialization. For this auto-
initialization SPI, the device operates in SPI master mode while the external memory
operates in slave mode.
output
HOLT INTEGRATED CIRCUITS
W
or as a level
pull-down resistor. Pin state is latched into the Operational Status register
MR
HI-6120, HI-6121
reset input, automatic initialization proceeds, copying configuration
MR
Refer to the data sheet section entitled “Reset and Initialization.”
, active high
Refer to the data sheet section entitled “Reset and Initialization.”
Internal 50K
pin. The Operational Status Register value (not these pins)
efer to the data sheet section entitled “Reset and Initialization.”
This SPI is separate from the host SPI found in the HI-6121.
output
Internal 50K
nternal 50K
3
Internal 50K
by the INTSEL bit in Configuration Register 1.
Operational Status Register description.
.
Internal 50K
Internal 50K
Internal 50K
W
DESCRIPTION
pull-down resistor.
This signal is programmed as a brief low-going
W
W
pull-up resistor.
W
pull-down resistor. If the AUTOEN pin is low,
MR
pull-down resistor. This input is
W
pin.
W
W
pull-down resistor.
pull-down resistor.
pull-down resistor.
Internal 50K
Internal 50K
If Operational Status register LOCK
Internal 50K
present on pins RTA4:0. Terminal
When Configuration Register 1
The host can also assert
via the dedicated auto-
W
W
W
pull-down resistor.
pull-up resistors.
pull-down resistors.
When this input is
When this pin is low,
If pin is high at
used to start
MR
The
reset