MT48H16M16LFBF-75:H Micron Technology Inc, MT48H16M16LFBF-75:H Datasheet - Page 37

• Manufacturer Part Number: MT48H16M16LFBF-75:H
• Description: SDRAM 256M-BIT 1.8V 54-PIN VFBGA
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H16M16LFBF-75:H

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 132MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 8/6ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 80mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4707290

Table 18: Truth Table – CKE
Notes 1–4 apply to all parameters and conditions
PDF: 09005aef834c13d2
256mb_mobile_sdram_y36n.pdf - Rev. I 11/09 EN
Current State
Power-down
Self refresh
Clock suspend
Deep power-down
Power-down
Deep power-down
Self refresh
Clock suspend
All banks idle
All banks idle
All banks idle
Reading or writing
Notes:
CKE
H
H
L
L
n-1
1. CKE
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time
6. Exiting self refresh at clock edge n will put the device in the all banks idle state after
7. After exiting clock suspend at clock edge n, the device will resume operation and recog-
8. Deep power-down is a power-saving feature of this device. This command is BURST TER-
ous clock edge.
MAND
for clock edge n + 1 (provided that
t
occurring during the
during the
nize the next command at clock edge n + 1.
MINATE when CKE is HIGH and DEEP POWER-DOWN when CKE is LOW.
XSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges
CKE
H
H
L
L
n
n
is the logic state of CKE at clock edge n; CKE
n
.
t
n
XSR period.
is the command registered at clock edge n, and ACTION
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
BURST TERMINATE
Table 17 (page 35)
t
XSR period. A minimum of two NOP commands must be provided
AUTO REFRESH
Command
37
VALID
X
X
X
X
X
X
n
t
CKS is met).
Micron Technology, Inc. reserves the right to change products or specifications without notice.
n-1
Maintain deep power-down
Deep power-down entry
Maintain clock suspend
was the state of CKE at the previ-
Exit deep power-down
Maintain power-down
Maintain self refresh
Clock suspend entry
Power-down entry
Exit clock suspend
Exit power-down
Self refresh entry
Exit self refresh
Action
©2008 Micron Technology, Inc. All rights reserved.
n
n
is a result of COM-
Truth Tables
Notes
5
6
7
8