ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 154
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 154 of 826
- Download datasheet (20Mb)
21.3
21.4
21.4.1
21.4.2
32058J–AVR32–04/11
Block Diagram
Functional Description
Configuration
Memory Pointer
Each channel in the PDCA has a set of configuration registers. Among these are the Memory
Address Register (MAR), the Peripheral Select Register (PSR) and the Transfer Counter Regis-
ter (TCR). The 32-bit Memory Address Register must be programmed with the start address of
the memory buffer. The register will be automatically updated after each transfer to point to the
next location in memory. The Peripheral Select Register must be programmed to select the
desired peripheral/handshake interface. The Transfer Counter Register determines the number
of data items to be transferred. The counter will be decreased by one for each data item that has
been transferred.
Both the Memory Address Register and the Transfer Counter Register can be read at any time
to check the progress of the transfer.
Each channel has also reload registers for the Memory Address Register and the Transfer
Counter Register. When the TCR reaches zero, the values in the reload registers are loaded into
MAR and TCR. In this way, the PDCA can operate on two buffers for each channel.
Each channel has a 32-bit Memory Pointer Register (MAR). This register holds the memory
address for the next transfer to be performed. The register is automatically updated after each
Bus Matrix
Controller
Interrupt
HSB
HSB
IRQ
Peripheral DMA
HSB to PB
Controller
(PDCA)
Bridge
Handshake interfaces
Peripheral
Peripheral
Peripheral
Peripheral
(n-1)
0
1
2
AT32UC3A
154
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