ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 333

• Manufacturer Part Number: ATEVK1104
• Description: KIT DEV/EVAL FOR AVR32 AT32UC3A
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1104

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A3
• Data Bus Width: 32 bit
• Interface Type: USB, SPI, USART
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A3256
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.7.8
26.7.8.1
32058J–AVR32–04/11
SPI Mode
Modes of Operation
The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides com-
munication with external devices in Master or Slave Mode. It also enables communication
between processors if an external processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to
other SPIs. During a data transfer, one SPI system acts as the “master” which controls the data
flow, while the other devices act as “slaves'' which have data shifted into and out by the master.
Different CPUs can take turns being masters and one master may simultaneously shift data into
multiple slaves. (Multiple Master Protocol is the opposite of Single Master Protocol, where one
CPU is always the master while all of the others are always slaves.) However, only one slave
may drive its output to write data back to the master at any given time.
A slave device is selected when its NSS signal is asserted by the master. The USART in SPI
Master mode can address only one SPI Slave because it can generate only one NSS signal.
The SPI system consists of two data lines and two control lines:
• Master Out Slave In (MOSI): This data line supplies the output data from the master shifted
• Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of
• Serial Clock (CLK): This control line is driven by the master and regulates the flow of the data
• Slave Select (NSS): This control line allows the master to select or deselect the slave.
The USART can operate in Master Mode or in Slave Mode.
Operation in SPI Master Mode is programmed by writing at 0xE the MODE field in the Mode
Register. In this case the SPI lines must be connected as described below:
• the MOSI line is driven by the output pin TXD
• the MISO line drives the input pin RXD
• the CLK line is driven by the output pin CLK
• the NSS line is driven by the output pin RTS
Operation in SPI Slave Mode is programmed by writing at 0xF the MODE field in the Mode Reg-
ister. In this case the SPI lines must be connected as described below:
• the MOSI line drives the input pin RXD
• the MISO line is driven by the output pin TXD
• the CLK line drives the input pin CLK
• the NSS line drives the input pin CTS
In order to avoid unpredicted behavior, any change of the SPI Mode must be followed by a soft-
ware reset of the transmitter and of the receiver (except the initial configuration after a hardware
reset).
into the input of the slave.
the master.
bits. The master may transmit data at a variety of baud rates. The CLK line cycles once for
each bit that is transmitted.
AT32UC3A
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