ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 307

• Manufacturer Part Number: ATEVK1104
• Description: KIT DEV/EVAL FOR AVR32 AT32UC3A
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1104

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A3
• Data Bus Width: 32 bit
• Interface Type: USB, SPI, USART
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A3256
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.7.1.3
Figure 26-4. Fractional Baud Rate Generator
26.7.1.4
32058J–AVR32–04/11
CLK_USART/DIV
CLK
CLK_USART
Reserved
Fractional Baud Rate in Asynchronous Mode
Baud Rate in Synchronous Mode or SPI Mode
USCLKS
1
2
3
0
The Baud Rate generator previously defined is subject to the following limitation: the output fre-
quency changes by only integer multiples of the reference frequency. An approach to this
problem is to integrate a fractional N clock generator that has a high resolution. The generator
architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock.
This fractional part is programmed with the FP field in the Baud Rate Generator Register
(BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock
divider. This feature is only available when using USART normal mode. The fractional Baud
Rate is calculated using the following formula:
The modified architecture is presented below:
If the USART is programmed to operate in synchronous mode, the selected clock is simply
divided by the field CD in BRGR.
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided
directly by the signal on the USART CLK pin. No division is active. The value written in BRGR
Baudrate
BaudRate
16-bit Counter
CD
=
---------------------------------------------------------------- - -
⎛
⎝
8 2 Over
Modulus
=
Control
(
FP
SelectedClock
------------------------------------- - -
SelectedClock
–
CD
) CD
⎛
⎝
+
USCLKS = 3
glitch-free
FP
------ -
FP
logic
8
⎞
⎠
⎞
⎠
SYNC
0
CD
>1
0
1
0
1
OVER
Sampling
Divider
FIDI
AT32UC3A
0
1
SYNC
CLK
BaudRate
Sampling
Clock
Clock
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