ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 511
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 511 of 826
- Download datasheet (20Mb)
30.7.2
30.7.2.1
30.7.2.2
Figure 30-13. Device Mode States
30.7.2.3
32058J–AVR32–04/11
USB Device Operation
Introduction
Power-On and Reset
USB Reset
In device mode, the USB controller supports full- and low-speed data transfers.
In addition to the default control endpoint, six endpoints are provided, which can be configured
with the types isochronous, bulk or interrupt, as described in
The device mode starts in the Idle state, so the pad consumption is reduced to the minimum.
Figure 30-13
After a hardware reset, the USB controller device mode is in the Reset state. In this state:
D+ or D- will be pulled up according to the selected speed as soon as the DETACH bit is cleared
and VBus is present. See
When the USB macro is enabled (USBE = 1) in device mode (ID = 1), its device mode state
goes to the Idle state with minimal power consumption. This does not require the USB clock to
be activated.
The USB controller device mode can be disabled and reset at any time by disabling the USB
macro (USBE = 0) or when host mode is engaged (ID = 0).
The USB bus reset is managed by hardware. It is initiated by a connected host.
When a USB reset is detected on the USB line, the following operations are performed by the
controller:
•the macro clock is stopped in order to minimize power consumption (FRZCLK = 1);
•the internal registers of the device mode are reset;
•the endpoint banks are de-allocated;
•neither D+ nor D- is pulled up (DETACH = 1).
•all the endpoints are disabled, except the default control endpoint;
•the default control endpoint is reset (see
•the data toggle sequence of the default control endpoint is cleared;
•at the end of the reset process, the End of Reset interrupt (EORST) is raised.
describes the USB controller device mode main states.
RESET
HW
| ID = 0
USBE = 0
Section 30.7.1.5.1 on page 506
Reset
| ID = 0
& ID = 1
USBE = 0
state>
other
<any
USBE = 1
Section 30.7.2.4 on page 512
Idle
for further details.
Table 30-1 on page
for more details);
AT32UC3A
497.
511
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