ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 527
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 527 of 826
- Download datasheet (20Mb)
Figure 30-27. Example of an OUT Pipe with 1 Data Bank
Figure 30-28. Example of an OUT Pipe with 2 Data Banks and no Bank Switching Delay
Figure 30-29. Example of an OUT Pipe with 2 Data Banks and a Bank Switching Delay
30.7.3.12
32058J–AVR32–04/11
TXOUTI
FIFOCON
TXOUTI
FIFOCON
TXOUTI
FIFOCON
CRC Error
SW
SW
write data to CPU
SW
This error exists only for isochronous IN pipes. It raises the CRC Error interrupt (CRCERRI),
what triggers a PXINT interrupt if CRCERRE = 1.
A CRC error can occur during IN stage if the USB controller detects a corrupted received packet.
The IN packet is stored in the bank as if no CRC error had occurred (RXINI is raised).
write data to CPU
write data to CPU
BANK 0
BANK 0
BANK 0
SW
SW
SW
OUT
OUT
OUT
SW
SW
write data to CPU
(bank 0)
write data to CPU
DATA
BANK 1
(bank 0)
DATA
(bank 0)
BANK 1
DATA
ACK
HW
SW
HW
ACK
HW
ACK
SW
OUT
SW
SW
OUT
write data to CPU
SW
write data to CPU
(bank 1)
write data to CPU
DATA
BANK0
BANK 0
BANK0
(bank 1)
DATA
ACK
AT32UC3A
SW
OUT
ACK
527
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