ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 156

• Manufacturer Part Number: ATEVK1104
• Description: KIT DEV/EVAL FOR AVR32 AT32UC3A
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1104

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A3
• Data Bus Width: 32 bit
• Interface Type: USB, SPI, USART
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A3256
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.4.9
21.4.10
21.5
21.5.1
Table 21-1.
21.5.2
32058J–AVR32–04/11
Offset
0x0C
0x1C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
User Interface
0x00C0 - 0x00FF
0x0000 - 0x003F
0x0040 - 0x007F
0x0080 - 0x00BF
0x0100 - 0x013F
Address Range
Priority
Error Handling
Memory Map Overview
Channel Memory Map
Register Map Overview
-
-
Memory Address Reload Register
Transfer Counter Reload Register
If more then one PDCA channel is requesting transfer at a given time, the PDCA channels are
prioritized by their channel number. Channels with lower numbers have priority over channels
with higher numbers, giving channel 0 the highest priority.
If the memory address is set to point to an invalid location in memory, an error will occur when
the PDCA tries to perform a transfer. When an error occurs, the Transfer Error flag (TERR) in
the Interrupt Status Register will be set and the DMA channel that caused the error will be
stopped. In order to restart the channel, the user must program the Memory Address Register to
a valid address and then write the Error Clear bit (ECLR) in the Control Register (CR) to ‘1’. An
interrupt can optionally be triggered on errors by writing the TERR-bit in the Interrupt Enable
Register (IER) to ‘1’.
Note:
Memory Address Register
Peripheral Select Register
Transfer Counter Register
Interrupt Enable Register
Control Register
Status Register
Mode Register
The number of channels is implementation specific. See part documentation for details.
Register
DMA channel n-1 configuration registers
DMA channel 0 configuration registers
DMA channel 1 configuration registers
DMA channel 2 configuration registers
DMA channel 3 configuration registers
DMA channel 4 configuration registers
Register Name
MARR
TCRR
MAR
PSR
TCR
MR
IER
CR
SR
Contents
-
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read-only
Write-only
Write-only
Access
AT32UC3A
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
*
-
-
156