ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 517
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 517 of 826
- Download datasheet (20Mb)
Figure 30-18. Example of an IN Endpoint with 2 Data Banks
30.7.2.12.2 Detailed Description
32058J–AVR32–04/11
TXINI
FIFOCON
SW
write data to CPU
The data is written by the firmware, following the next flow:
If the endpoint uses several banks, the current one can be written by the firmware while the pre-
vious one is being read by the host. Then, when the firmware clears FIFOCON, the following
bank may already be free and TXINI is set immediately.
An “Abort” stage can be produced when a zero-length OUT packet is received during an IN
stage of a control or isochronous IN transaction. The KILLBK bit is used to kill the last written
bank. The best way to manage this abort is to apply the algorithm represented on
•when the bank is empty, TXINI and FIFOCON are set, what triggers an EPXINT interrupt if
•the firmware acknowledges the interrupt by clearing TXINI;
•the firmware writes the data into the current bank by using the USB Pipe/Endpoint X FIFO
•the firmware allows the controller to send the bank and switches to the next bank (if any) by
BANK 0
TXINE = 1;
Data register (USB_FIFOX_DATA), until all the data frame is written or the bank is full (in
which case RWALL is cleared by hardware and BYCT reaches the endpoint size);
clearing FIFOCON.
SW
IN
SW
write data to CPU
BANK 1
(bank 0)
DATA
SW
HW
ACK
SW
write data to CPU
IN
BANK0
(bank 1)
DATA
AT32UC3A
ACK
Figure
30-19.
517
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