ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 425
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 425 of 826
- Download datasheet (20Mb)
28.8.1
Register Name:
Access Type:
Reset Value:
•
This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed.
Table 28-9.
32058J–AVR32–04/11
MODE: SDRAMC Command Mode
0
0
0
0
1
1
1
31
23
15
MODE
–
–
–
7
–
0
0
1
1
0
0
1
SDRAMC Mode Register
0
1
0
1
0
1
0
Description
Normal mode. Any access to the SDRAM is decoded normally.
The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle.
The SDRAM Controller issues an “All Banks Precharge” command when the SDRAM device is accessed
regardless of the cycle.
The SDRAM Controller issues a “Load Mode Register” command when the SDRAM device is accessed
regardless of the cycle. The command will load the CAS latency from the Configuration Register and every other
value set to 0 into the Mode Register.
The SDRAM Controller issues an “Auto-Refresh” Command when the SDRAM device is accessed regardless of
the cycle. Previously, an “All Banks Precharge” command must be issued.
The SDRAM Controller issues an extended load mode register command when the SDRAM device is accessed
regardless of the cycle. The command will load the PASR, DS and TCR from the Low Power Register and every
other value set to 0 into the Extended Mode Register.
Deep power-down mode. Enters deep power-down mode.
30
22
14
–
–
–
6
–
29
21
13
–
–
–
5
–
MR
Read/Write
0x00000000
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
MODE
25
17
–
–
9
–
1
AT32UC3A
24
16
–
–
8
–
0
425
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