ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 520
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 520 of 826
- Download datasheet (20Mb)
30.7.2.15
30.7.2.16
30.7.2.17
30.7.2.17.1 Global Interrupts
32058J–AVR32–04/11
CRC Error
Interrupts
Overflow
An underflow can not occur during OUT stage on a CPU action, since the firmware may read
only if the bank is not empty (RXOUTI = 1 or RWALL = 1).
An underflow can also occur during OUT stage if the host sends a packet while the bank is
already full. Typically, the CPU is not fast enough. The packet is lost.
An underflow can not occur during IN stage on a CPU action, since the firmware may write only
if the bank is not full (TXINI = 1 or RWALL = 1).
This error exists for all endpoint types. It raises the Overflow interrupt (OVERFI), what triggers
an EPXINT interrupt if OVERFE = 1.
An overflow can occur during OUT stage if the host attempts to write into a bank that is too small
for the packet. The packet is acknowledged and the Received OUT Data interrupt (RXOUTI) is
raised as if no overflow had occurred. The bank is filled with all the first bytes of the packet that
fit in.
An overflow can not occur during IN stage on a CPU action, since the firmware may write only if
the bank is not full (TXINI = 1 or RWALL = 1).
This error exists only for isochronous OUT endpoints. It raises the CRC Error interrupt
(CRCERRI), what triggers an EPXINT interrupt if CRCERRE = 1.
A CRC error can occur during OUT stage if the USB controller detects a corrupted received
packet. The OUT packet is stored in the bank as if no CRC error had occurred (RXOUTI is
raised).
See the structure of the USB device interrupt system on
There are two kinds of device interrupts: processing, i.e. their generation is part of the normal
processing, and exception, i.e. errors (not related to CPU exceptions).
The processing device global interrupts are:
The exception device global interrupts are:
•the Suspend interrupt (SUSP);
•the Start of Frame interrupt (SOF) with no frame number CRC error (FNCERR = 0);
•the End of Reset interrupt (EORST);
•the Wake-Up interrupt (WAKEUP);
•the End of Resume interrupt (EORSM);
•the Upstream Resume interrupt (UPRSM);
•the Endpoint X interrupt (EPXINT);
•the DMA Channel X interrupt (DMAXINT).
•the Start of Frame interrupt (SOF) with a frame number CRC error (FNCERR = 1).
Figure 30-6 on page
AT32UC3A
504.
520
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