ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 400
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 400 of 826
- Download datasheet (20Mb)
Figure 27-34. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow
27.6.9
27.6.9.1
32058J–AVR32–04/11
Internal signal from PM
Slow Clock Mode
NBS0, NBS1,
Asynchronous Page Mode
A0, A1
CLK_SMC
Protocol and Timings in Page Mode
A[25:2]
Clock Mode
NWE
NCS
The SMC supports asynchronous burst reads in page mode, providing that the page mode is
enabled in the MODE register (PMEN field). The page size must be configured in the MODE
register (PS field) to 4, 8, 16 or 32 bytes.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte
page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The
MSB of data address defines the address of the page in memory, the LSB of address define the
address of the data in the page as detailed in
With page mode memory devices, the first access to one page (t
quent accesses to the page (t
enables the user to define different read timings for the first access within one page, and next
accesses within the page.
Table 27-5.
Notes:
Figure 27-35
SLOW CLOCK MODE WRITE
Page Size
4 bytes
8 bytes
16 bytes
32 bytes
1
1. A denotes the address bus of the memory device
2. For 16-bit devices, the bit 0 of address is ignored. For 32-bit devices, bits [1:0] are ignored.
1
shows the NRD and NCS timings in page mode access.
Page Address and Data Address within a Page
Page Address
A[25:2]
A[25:3]
A[25:4]
A[25:5]
1
sa
) as shown in
(1)
IDLE STATE
Table
Figure
Reload Configuration
27-5.
Data Address in the Page
A[1:0]
A[2:0]
A[3:0]
A[4:0]
Wait State
27-35. When in page mode, the SMC
2
pa
NORMAL MODE WRITE
) takes longer than the subse-
3
AT32UC3A
(2)
2
400
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