ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 398

• Manufacturer Part Number: ATEVK1104
• Description: KIT DEV/EVAL FOR AVR32 AT32UC3A
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1104

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A3
• Data Bus Width: 32 bit
• Interface Type: USB, SPI, USART
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A3256
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.6.8
27.6.8.1
Figure 27-32. Read/write Cycles in Slow Clock Mode
32058J–AVR32–04/11
NBS0, NBS1,
A0, A1
CLK_SMC
A[25:2]
NWE
NCS
Slow Clock Mode
Slow Clock Mode Waveforms
SLOW CLOCK MODE WRITE
1
NWE_CYCLES = 3
The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when
an internal signal driven by the Power Management Controller is asserted because CLK_SMC
has been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-pro-
grammed waveforms are ignored and the slow clock mode waveforms are applied. This mode is
provided so as to avoid reprogramming the User Interface with appropriate waveforms at very
slow clock rate. When activated, the slow mode is active on all chip selects.
Figure 27-32
chip selects. indicates the value of read and write parameters in slow clock mode.
Table 27-4.
Read Parameters
NRD_SETUP
NRD_PULSE
NCS_RD_SETUP
NCS_RD_PULSE
NRD_CYCLE
1
illustrates the read and write operations in slow clock mode. They are valid on all
Read and Write Timing Parameters in Slow Clock Mode
1
Duration (cycles)
0
2
1
1
2
Write Parameters
NWE_SETUP
NWE_PULSE
NCS_WR_SETUP
NCS_WR_PULSE
NWE_CYCLE
NBS0, NBS1,
A0, A1
CLK_SMC
A[25:2]
NRD
NCS
SLOW CLOCK MODE READ
NRD_CYCLES = 2
1
Duration (cycles)
AT32UC3A
1
1
0
3
3
1
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