DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 149

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–81. EP3SL200 Column Pins Input Timing Parameters (Part 4 of 4)
Table 1–82. EP3SL200 Row Pins Input Timing Parameters (Part 1 of 3)
© July 2010 Altera Corporation
3.0-V
PCI-X
3.3-V
LVTTL
3.3-V
LVCMOS
3.0-V
LVTTL
3.0-V
LVCMOS
2.5 V
1.8 V
Standard
Standard
I/O
I/O
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
Clock
PLL
PLL
PLL
PLL
PLL
PLL
PLL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Table 1–82
standards.
su
su
su
su
su
su
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
h
h
h
h
h
h
Industrial
Industrial
-1.148
-1.476
1.296
1.789
-1.298
-0.638
-1.298
-0.638
-1.304
-0.632
-1.304
-0.632
-1.292
-0.644
-1.322
-1.312
1.432
0.915
1.432
0.915
1.438
0.909
1.438
0.909
1.426
0.921
0.891
1.457
Fast Model
Fast Model
lists the EP3SL200 row pins input timing parameters for single-ended I/O
Commercial
Commercial
-1.184
-1.476
1.330
1.789
-1.321
-0.643
-1.321
-0.643
-1.332
-0.632
-1.332
-0.632
-1.325
-0.639
-1.354
-1.343
1.473
0.938
1.473
0.938
1.484
0.927
1.484
0.927
1.477
0.934
0.902
1.507
-1.809 -1.777 -2.001 -1.933 -2.481 -1.777 -2.001
-2.237 -2.273 -2.557 -2.476 -2.996 -2.273 -2.557
2.031
2.726
1.1 V
V
-1.972 -1.978 -2.368 -2.291 -2.712 -2.132 -2.388 -2.291 -2.712
-1.972 -1.978 -2.368 -2.291 -2.712 -2.132 -2.388 -2.291 -2.712
-1.972 -1.978 -2.368 -2.291 -2.712 -2.132 -2.388 -2.291 -2.712
-1.969 -1.979 -2.371 -2.294 -2.715 -2.131 -2.393 -2.294 -2.715
-1.969 -1.979 -2.371 -2.294 -2.715 -2.131 -2.393 -2.294 -2.715
-1.978 -1.992 -2.386 -2.309 -2.730 -2.140 -2.403 -2.309 -2.730
-2.017 -2.051 -2.384 -2.307 -2.728 -2.173 -2.404 -2.307 -2.728
-1.993 -2.019 -2.316 -2.239 -2.660 -2.142 -2.339 -2.239 -2.660
C2
1.671
2.210
1.671
2.210
2.207
1.674
2.207
2.216
1.665
2.216
1.625
2.254
1.625
1.649
2.230
1.728
CCL
1.1 V
V
C2
CCL
=
=
2.010
2.778
1.1 V
V
C3
1.862
2.223
1.862
2.223
2.224
1.861
2.224
2.237
1.848
2.237
1.722
2.297
1.722
1.754
2.265
1.855
CCL
1.1 V
V
C3
CCL
=
=
2.258
3.112
1.1 V
V
1.969
2.633
1.969
2.633
2.636
1.966
2.636
2.651
1.951
2.651
1.945
2.649
1.945
2.013
2.581
2.172
C4
CCL
1.1 V
V
C4
CCL
=
=
2.176
2.999
1.1 V
V
1.850
2.541
1.850
2.541
2.544
1.847
2.544
2.559
1.832
2.559
1.834
2.557
1.834
1.902
2.489
2.061
CCL
1.1 V
V
CCL
=
=
C4L
C4L
2.723
3.542
0.9 V
V
1.775
2.966
1.775
2.966
2.969
1.772
2.969
2.984
1.757
2.984
1.742
2.982
1.742
1.810
2.914
1.969
CCL
0.9 V
V
CCL
Stratix III Device Handbook, Volume 2
=
=
2.010
2.778
1.1 V
V
1.751
2.384
1.751
2.384
2.383
1.752
2.383
2.392
1.743
2.392
1.710
2.425
1.710
1.741
2.394
1.837
1.1 V
CCL
V
I3
I3
CCL
=
=
2.258
3.112
1.1 V
V
1.869
2.665
1.869
2.665
2.670
1.864
2.670
2.680
1.854
2.680
1.853
2.681
1.853
1.918
2.616
2.073
1.1 V
V
I4
CCL
I4
CCL
=
=
-1.933
-2.476
2.176
2.999
1.850
2.541
1.850
2.541
2.544
1.847
2.544
2.559
1.832
2.559
1.834
2.557
1.834
1.902
2.489
2.061
1.1 V
V
1.1 V
V
CCL
CCL
1–149
=
=
I4L
I4L
-2.481
-2.996
1.775
2.966
1.775
2.966
2.969
1.772
2.969
2.984
1.757
2.984
1.742
2.982
1.742
1.810
2.914
1.969
2.723
3.542
0.9 V
0.9 V
V
V
CCL
CCL
=
=
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns