DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 320
DK-DEV-3SL150N
Manufacturer Part Number
DK-DEV-3SL150N
Description
KIT DEVELOPMENT STRATIX III
Manufacturer
Altera
Series
Stratix® IIIr
Type
FPGAr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.DK-DEV-3SL150N.pdf
(34 pages)
Specifications of DK-DEV-3SL150N
Contents
Development Platform, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP3S
Silicon Family Name
Stratix III
Kit Contents
Development Board, Cable And Accessories
Rohs Compliant
Yes
For Use With/related Products
EP3SL150F152
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2568
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-3SL150N
Manufacturer:
Altera
Quantity:
135
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Table 1–180. EP3SE50 Column Pin Regional Clock Timing Specifications
Table 1–181. EP3SE50 Row Pin Regional Clock Timing Specifications
Table 1–182. EP3SE50 Column Pin Periphery Clock Timing Specifications
Table 1–183. EP3SE50 Row Pin Periphery Clock Timing Specifications
Stratix III Device Handbook, Volume 2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Parameter
Parameter
Parameter
Parameter
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
Industrial
Industrial
Industrial
Industrial
-0.062
-0.047
-0.047
-0.021
-0.103
1.711
1.711
0.034
0.106
1.640
1.558
0.020
1.472
1.472
1.467
1.385
Fast Model
Fast Model
Fast Model
Fast Model
Table 1–180
devices.
Table 1–182
devices.
Commercial
Commercial
Commercial
Commercial
-0.044
-0.044
-0.055
1.721
1.721
0.038
0.102
1.732
1.641
0.091
0.000
1.481
1.481
1.543
1.452
0.036
and
and
Table 1–181
Table 1–183
-0.193 -0.255 -0.212
-0.074 -0.101 -0.212
-0.168 -0.241 -0.208
-0.310 -0.404 -0.389
-0.288 -0.347 -0.302
-0.288 -0.347 -0.302
-0.231 -0.307 -0.282
-0.373 -0.470 -0.463
2.429
2.429
2.361
2.219
2.155
2.155
2.208
2.063
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C2
C2
C2
C2
CCL
CCL
CCL
CCL
=
=
=
=
2.679
2.679
2.580
2.417
2.417
2.417
2.472
2.309
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C3
C3
C3
C3
CCL
CCL
CCL
CCL
list the regional clock timing parameters for EP3SE50
list the periphery clock timing parameters for EP3SE50
=
=
=
=
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
3.053
3.053
2.905
2.724
2.825
2.825
2.843
2.662
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C4
C4
C4
C4
CCL
CCL
CCL
CCL
=
=
=
=
-0.168
-0.168
-0.155
-0.326
-0.266
-0.266
-0.230
-0.401
2.767
2.767
2.810
2.639
2.681
2.681
2.729
2.558
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
C4L
C4L
C4L
C4L
-0.210
-0.369
-0.079
-0.079
-0.301
-0.460
3.191
3.191
2.977
2.818
3.247
3.247
3.012
2.853
0.040
0.040
0.9 V
0.9 V
0.9 V
0.9 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
-0.255
-0.101
-0.191
-0.361
-0.347
-0.347
-0.262
-0.432
2.679
2.679
2.636
2.466
2.417
2.417
2.521
2.351
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
I3
CCL
I3
CCL
I3
CCL
I3
CCL
=
=
=
=
© July 2010 Altera Corporation
3.053
3.053
0.263
0.263
2.960
2.771
0.321
0.132
2.819
2.819
0.300
0.300
2.891
2.702
0.372
0.183
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
I4
CCL
I4
CCL
I4
CCL
I4
CCL
=
=
=
=
-0.168
-0.168
-0.108 -0.264
-0.287 -0.423
-0.266 -0.079
-0.266 -0.079
-0.184 -0.361
-0.363 -0.520
2.767
2.767
2.868
2.689
2.681
2.681
2.771
2.592
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
I4L
I4L
I4L
I4L
I/O Timing
3.191
3.191
0.040
0.040
3.003
2.844
3.247
3.247
3.028
2.869
0.9 V
0.9 V
0.9 V
0.9 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
Units
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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