DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 86

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–86
Table 1–57. EP3SL70 Column Pins Output Timing Parameters (Part 1 of 4)
Stratix III Device Handbook, Volume 2
LVDS_E_1R
LVDS_E_3R
MINI-
LVDS_E_1R
MINI-
LVDS_E_3R
RSDS_E_1R
RSDS_E_3R
DIFFERENTIAL
1.2-V HSTL
CLASS I
DIFFERENTIAL
1.2-V HSTL
CLASS II
I/O Standard
10mA
12mA
16mA
4mA
6mA
8mA
—
—
—
—
—
—
Table 1–57
I/O standards.
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
lists the EP3SL70 column pins output timing parameters for differential
Industrial
3.029
3.025
3.029
3.025
3.029
3.025
3.056
3.046
3.046
3.039
3.038
3.060
3.050
3.045
3.043
3.035
3.036
3.035
3.047
3.043
3.033
3.031
3.031
3.035
Fast Model
Commercial
3.246
3.249
3.246
3.249
3.246
3.249
3.279
3.269
3.269
3.263
3.261
3.283
3.272
3.268
3.266
3.257
3.259
3.256
3.269
3.266
3.255
3.253
3.254
3.257
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631
4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697
4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631
4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697
4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631
4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697
4.646 5.054 5.571 5.431 5.649 5.181 5.698 5.560 5.717
4.636 5.043 5.561 5.421 5.639 5.170 5.688 5.550 5.707
4.639 5.047 5.565 5.425 5.643 5.175 5.693 5.555 5.712
4.632 5.041 5.559 5.419 5.637 5.168 5.687 5.549 5.706
4.629 5.038 5.556 5.416 5.634 5.165 5.683 5.545 5.702
4.650 5.058 5.575 5.435 5.653 5.185 5.703 5.565 5.722
4.629 5.035 5.550 5.410 5.628 5.161 5.676 5.538 5.695
4.629 5.035 5.551 5.411 5.629 5.162 5.678 5.540 5.697
4.628 5.034 5.549 5.409 5.627 5.161 5.677 5.539 5.696
4.618 5.024 5.540 5.400 5.618 5.151 5.667 5.529 5.686
4.624 5.031 5.548 5.408 5.626 5.159 5.676 5.538 5.695
4.607 5.012 5.526 5.386 5.604 5.138 5.652 5.514 5.671
4.625 5.030 5.544 5.404 5.622 5.157 5.671 5.533 5.690
4.626 5.032 5.548 5.408 5.626 5.159 5.675 5.537 5.694
4.615 5.021 5.536 5.396 5.614 5.148 5.663 5.525 5.682
4.613 5.018 5.534 5.394 5.612 5.146 5.661 5.523 5.680
4.616 5.023 5.539 5.399 5.617 5.150 5.667 5.529 5.686
4.613 5.018 5.533 5.393 5.611 5.145 5.660 5.522 5.679
1.1 V
V
C2
CCL
=
1.1 V
V
C3
CCL
=
1.1 V
V
C4
CCL
=
1.1 V
V
CCL
=
C4L
© July 2010 Altera Corporation
0.9 V
V
CCL
=
1.1 V
V
I3
CCL
=
1.1 V
V
I4
CCL
I/O Timing
=
1.1 V
V
CCL
=
I4L
0.9 V
V
CCL
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns