DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 285

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–131. EP3SE260 Column Pins Input Timing Parameters (Part 3 of 3)
Table 1–132. EP3SE260 Row Pins Input Timing Parameters (Part 1 of 3)
© July 2010 Altera Corporation
1.2-V HSTL
CLASS I
1.2-V HSTL
CLASS II
3.0-V PCI
3.0-V
PCI-X
3.3-V
LVTTL
3.3-V
LVCMOS
3.0-V
LVTTL
Standard
Standard
I/O
I/O
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
PLL
PLL
PLL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
Table 1–132
standards.
t
t
t
t
t
t
t
t
h
h
h
h
h
h
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
Industrial
Industrial
-1.219
-0.704
-1.219
-0.704
-1.225
-0.698
1.355
0.983
1.355
0.983
1.361
0.977
-1.162
-1.335
-1.150
-1.323
-1.150
-1.323
-1.253
-1.428
1.310
1.652
1.298
1.640
1.298
1.640
1.399
1.743
Fast Model
Fast Model
lists the EP3SE260 row pins input timing parameters for single-ended I/O
Commercial
Commercial
-1.374
-0.685
-1.374
-0.685
-1.385
-0.674
-1.106
-1.385
-1.094
-1.373
-1.094
-1.373
-1.197
-1.476
1.524
0.983
1.524
0.983
1.535
0.972
1.254
1.700
1.242
1.688
1.242
1.688
1.343
1.789
-2.059 -1.988 -2.283 -2.177 -2.643 -2.003 -2.382 -2.177 -2.643
-2.059 -1.988 -2.283 -2.177 -2.643 -2.003 -2.382 -2.177 -2.643
-2.059 -1.988 -2.283 -2.177 -2.643 -2.003 -2.382 -2.177 -2.643
-2.056 -1.989 -2.286 -2.180 -2.646 -2.002 -2.387 -2.180 -2.646
-2.056 -1.989 -2.286 -2.180 -2.646 -2.002 -2.387 -2.180 -2.646
-1.718 -1.799 -1.954 -1.818 -2.253 -1.799 -1.954 -1.818 -2.253
-2.134 -2.076 -2.328 -2.245 -2.809 -2.076 -2.328 -2.245 -2.809
-1.708 -1.788 -1.938 -1.802 -2.237 -1.788 -1.938 -1.802 -2.237
-2.124 -2.065 -2.312 -2.229 -2.793 -2.065 -2.312 -2.229 -2.793
-1.708 -1.788 -1.938 -1.802 -2.237 -1.788 -1.938 -1.802 -2.237
-2.124 -2.065 -2.312 -2.229 -2.793 -2.065 -2.312 -2.229 -2.793
-1.821 -1.917 -2.183 -2.049 -2.481 -1.917 -2.183 -2.049 -2.481
-2.237 -2.191 -2.557 -2.476 -3.037 -2.191 -2.557 -2.476 -3.037
1.749
2.293
1.749
2.293
2.290
1.752
2.290
1.940
2.622
1.930
2.612
1.930
2.612
2.044
2.726
1.1 V
1.1 V
V
V
C2
CCL
C2
CCL
=
=
1.864
2.233
1.864
2.233
2.234
1.863
2.234
2.027
2.581
2.016
2.570
2.016
2.570
2.148
2.699
1.1 V
V
1.1 V
V
C3
C3
CCL
CCL
=
=
1.862
2.553
1.862
2.553
2.556
1.859
2.556
2.204
2.880
2.188
2.864
2.188
2.864
2.436
3.112
1.1 V
1.1 V
V
V
C4
C4
CCL
CCL
=
=
1.767
2.431
1.767
2.431
2.434
1.764
2.434
2.052
2.767
2.036
2.751
2.036
2.751
2.284
2.999
1.1 V
1.1 V
V
V
CCL
CCL
=
=
C4L
C4L
1.884
2.902
1.884
2.902
2.905
1.881
2.905
2.490
3.350
2.474
3.334
2.474
3.334
2.723
3.583
0.9 V
0.9 V
V
V
CCL
CCL
Stratix III Device Handbook, Volume 2
=
=
1.864
2.260
1.864
2.260
2.259
1.865
2.259
2.027
2.581
2.016
2.570
2.016
2.570
2.148
2.699
1.1 V
1.1 V
V
V
CCL
I3
CCL
I3
=
=
2.204
2.880
2.188
2.864
2.188
2.864
2.436
3.112
1.883
2.659
1.883
2.659
2.664
1.878
2.664
1.1 V
1.1 V
V
V
CCL
I4
CCL
I4
=
=
2.052
2.767
2.036
2.751
2.036
2.751
2.284
2.999
1.767
2.431
1.767
2.431
2.434
1.764
2.434
1.1 V
1.1 V
V
V
CCL
CCL
1–285
=
=
I4L
I4L
2.490
3.350
2.474
3.334
2.474
3.334
2.723
3.583
1.884
2.902
1.884
2.902
2.905
1.881
2.905
0.9 V
V
0.9 V
V
CCL
CCL
=
=
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns