DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 25
DK-DEV-3SL150N
Manufacturer Part Number
DK-DEV-3SL150N
Description
KIT DEVELOPMENT STRATIX III
Manufacturer
Altera
Series
Stratix® IIIr
Type
FPGAr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.DK-DEV-3SL150N.pdf
(34 pages)
Specifications of DK-DEV-3SL150N
Contents
Development Platform, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP3S
Silicon Family Name
Stratix III
Kit Contents
Development Board, Cable And Accessories
Rohs Compliant
Yes
For Use With/related Products
EP3SL150F152
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2568
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-3SL150N
Manufacturer:
Altera
Quantity:
135
- Current page: 25 of 332
- Download datasheet (4Mb)
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Switching Characteristics
Figure 1–3. LVDS Soft-CDR/DPA Sinusiodal Jitter Tolerance Specification for Stratix III Devices
© July 2010 Altera Corporation
f
Figure 1–3
for Stratix III devices.
Table 1–27
devices.
Table 1–27. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for Stratix III Devices
External Memory Interface Specifications
The following sections describe the external memory I/O timing specifications and
the DLL and DQS block specifications.
For more information about the maximum clock rate support for external memory
interfaces with a half-rate or full-rate controller, refer to
Specifications
External Memory I/O Timing Specifications
Table 1–28
write data paths. Use these specifications to determine timing margins for source
synchronous paths between the Stratix III FPGA and the external memory device. For
more information, refer to the figure for “SW (sampling window)” in the
on page
F1
F2
F3
F4
1–326.
shows the LVDS Soft-CDR/ DPA sinusoidal jitter tolerance specifications
lists the LVDS Soft-CDR/ DPA sinusiodal jitter mask values for Stratix III
and
Jitter Frequency (Hz)
of the External Memory Interfaces Handbook.
Table 1–29
50,000,000
1,493,000
list Stratix III device timing uncertainties on the read and
10,000
17,565
Jitter Amplitude
25.000
25.000
0.350
0.350
Section III: System Performance
Stratix III Device Handbook, Volume 2
“Glossary”
Unit
UI
UI
UI
UI
1–25
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