DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 38

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–38
Programmable Output Buffer Delay
User I/O Pin Timing
Table 1–41. EP3SL50 Column Pins Input Timing Parameters (Part 1 of 3)
Stratix III Device Handbook, Volume 2
3.3-V
LVTTL
3.3-V
LVCMOS
3.0-V
LVTTL
Standard
I/O
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
h
h
h
h
h
h
Table 1–40
of the output buffer. The default delay is 0 ps.
Table 1–40. Programmable Output Buffer Delay
Table 1–41
buffer t
non-PLL global clock (GCLK) and the PLL is driven by the global clock (GCLK-PLL).
For t
for each device to the GCLK/GCLK-PLL values for the device.
EP3SL50 I/O Timing Parameters
Table 1–41
devices for single-ended I/O standards.
Table 1–41
I/O standards.
D
Note to
(1) You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay
OUTBUF
Industrial
-0.690
-0.975
-0.690
-0.975
-0.701
-0.986
Control assignment to either positive, negative, or both edges with the specific values stated in this table for the
Output Buffer Delay assignment.
0.816
1.226
0.816
1.226
0.827
1.237
su
, t
Table
su
Symbol
h
Fast Model
, t
, and t
h
lists the delay chain settings that control the rising and falling edge delays
through
through
lists the EP3SL50 column pins input timing parameters for single-ended
, and t
1–40:
Commercial
-0.689
-0.975
-0.689
-0.975
-0.700
-0.986
co
0.814
1.226
0.814
1.226
0.825
1.237
using the regional clock, add the value from the adder tables listed
co
are reported for the cases when the I/O clock is driven by a
Table 1–140
Table 1–44
Rising and/or Falling
Edge delay
-1.004 -1.103 -1.311 -1.266 -1.627 -1.103 -1.311 -1.266 -1.627
-1.405 -1.532 -1.773 -1.713 -2.026 -1.532 -1.773 -1.713 -2.026
-1.004 -1.103 -1.311 -1.266 -1.627 -1.103 -1.311 -1.266 -1.627
-1.405 -1.532 -1.773 -1.713 -2.026 -1.532 -1.773 -1.713 -2.026
-1.003 -1.105 -1.310 -1.265 -1.626 -1.105 -1.310 -1.265 -1.626
-1.404 -1.534 -1.772 -1.712 -2.025 -1.534 -1.772 -1.712 -2.025
1.182
1.774
1.182
1.774
1.181
1.773
1.1 V
V
C2
CCL
Parameter
=
list the maximum I/O timing parameters for EP3SL50
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
list user I/O pin timing for Stratix III devices. I/O
1.304
1.947
1.304
1.947
1.306
1.949
1.1 V
V
C3
CCL
=
1.531
2.232
1.531
2.232
1.530
2.231
1.1 V
V
C4
CCL
(Note 1)
=
1.475
2.148
1.475
2.148
1.474
2.147
1.1 V
V
CCL
0 (default)
Typical
=
C4L
100
150
50
1.830
2.471
1.830
2.471
1.829
2.470
0.9 V
V
CCL
=
© July 2010 Altera Corporation
1.304
1.947
1.304
1.947
1.306
1.949
1.1 V
V
I3
CCL
=
1.531
2.232
1.531
2.232
1.530
2.231
1.1 V
V
I4
CCL
=
Unit
ps
ps
ps
ps
1.475
2.148
1.475
2.148
1.474
2.147
1.1 V
V
I/O Timing
CCL
=
I4L
1.830
2.471
1.830
2.471
1.829
2.470
0.9 V
V
CCL
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns