DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 65

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–48. EP3SL50 Row Pins Output Timing Parameters (Part 4 of 4)
Table 1–49. EP3SL50 Column Pin Delay Adders for Regional Clock
Table 1–50. EP3SL50 Row Pin Delay Adders for Regional Clock
© July 2010 Altera Corporation
DIFFERENTIAL
2.5-V
SSTL CLASS II
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
I/O Standard
Parameter
Parameter
16mA
Table 1–49
must be added to the GCLK values. Use these adder values to determine I/O timing
when the I/O pin is driven using the regional clock. This applies to all I/O standards
supported by Stratix III devices.
Table 1–49
Table 1–50
GCLK
GCLK
Clock
PLL
Industrial
Industrial
-0.068
-0.113
-0.107
0.239
0.008
1.614
0.111
0.101
Fast Model
Fast Model
t
t
co
co
and
lists the EP3SL50 column pin delay adders when using the regional clock.
lists the EP3SL50 row pin delay adders when using the regional clock.
Industrial
Commercial
Commercial
3.076
3.062
-0.127
-0.113
0.258
0.009
1.649
-0.07
0.124
0.107
Table 1–50
Fast Model
Commercial
3.311
3.295
-0.181 -0.196 -0.213 -0.205 -0.271 -0.199 -0.217 -0.209 -0.273
-0.164 -0.185 -0.213
0.341
0.014
2.575
1.1 V
-0.09
0.178
V
1.1 V
0.156
V
C2
C2
list the EP3SL50 regional clock (RCLK) adder values that
CCL
CCL
=
=
-0.092 -0.094 -0.091 -0.169 -0.086 -0.087
0.365
0.017
0.193
0.174
1.1 V
4.709 5.123 5.649 5.505 5.704 5.258 5.787 5.643 5.772
4.686 5.099 5.624 5.480 5.679 5.234 5.762 5.618 5.747
V
2.89
1.1 V
V
1.1 V
V
C3
C3
CCL
CCL
C2
CCL
=
=
=
3.164
0.208
0.019
0.194
1.1 V
V
1.1 V
1.1 V
V
0.39
V
C3
C4
C4
CCL
CCL
CCL
=
=
=
1.1 V
V
0.377
0.017
3.011
0.184
1.1 V
1.1 V
V
V
C4
-0.2
CCL
0.2
CCL
CCL
=
=
=
C4L
C4L
1.1 V
V
-0.266 -0.184 -0.212 -0.198 -0.262
0.263
0.251
0.439
CCL
0.9 V
0.9 V
3.22
V
V
0.02
CCL
CCL
=
C4L
Stratix III Device Handbook, Volume 2
=
=
0.9 V
V
CCL
0.375
2.908
0.197
0.018
0.177
1.1 V
1.1 V
V
V
I3
I3
CCL
=
CCL
=
=
1.1 V
V
CCL
I3
0.399
3.217
0.213
0.196
0.019
1.1 V
1.1 V
V
V
=
I4
I4
CCL
CCL
=
=
1.1 V
V
CCL
I4
0.203
0.188
0.388
0.017
3.063
-0.09
1.1 V
1.1 V
=
V
V
CCL
CCL
=
=
1–65
1.1 V
V
I4L
I4L
CCL
0.266
0.249
=
0.441
3.338
-0.17
0.9 V
0.9 V
V
V
0.02
I4L
CCL
CCL
=
=
0.9 V
V
CCL
=
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns