DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 217

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–104. EP3SE50 Row Pins Output Timing Parameters (Part 5 of 5)
Table 1–105. EP3SE50 Column Pins Input Timing Parameters (Part 1 of 3)
© July 2010 Altera Corporation
1.2-V
HSTL
CLASS I
3.0-V PCI
3.0-V
PCI-X
LVDS
MINI-LVDS
RSDS
DIFFERENTIAL
1.2-V HSTL
CLASS I
Standard
I/O Standard
I/O
4mA
6mA
8mA
—
—
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
PLL
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
PLL
PLL
Table 1–115
EP3SE50 devices for differential I/O standards.
Table 1–105
I/O standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
t
t
t
t
t
t
t
t
t
t
co
co
co
co
co
co
co
co
co
co
Industrial
-0.730
-0.867
-0.730
-0.867
-0.738
-0.859
-0.738
-0.859
0.848
1.120
0.848
1.120
0.856
1.112
0.856
1.112
Industrial
2.997
1.329
2.985
1.320
2.982
1.319
3.116
1.414
3.116
1.414
Fast Model
through
lists the EP3SE50 column pins input timing parameters for differential
Fast Model
Commercial
-0.751
-0.870
-0.751
-0.870
-0.763
-0.858
-0.763
-0.858
0.884
1.138
0.884
1.138
0.896
1.126
0.896
1.126
Table 1–108
Commercial
3.219
1.512
3.207
1.504
3.205
1.504
3.340
1.598
3.340
1.598
-1.114 -1.228 -1.341 -1.284 -1.581 -1.230 -1.344 -1.290 -1.617
-1.397 -1.578 -1.752 -1.669 -1.666 -1.580 -1.754 -1.665 -1.710
-1.114 -1.228 -1.341 -1.284 -1.581 -1.230 -1.344 -1.290 -1.617
-1.397 -1.578 -1.752 -1.669 -1.666 -1.580 -1.754 -1.665 -1.710
-1.124 -1.239 -1.357 -1.300 -1.597 -1.241 -1.359 -1.305 -1.632
-1.387 -1.567 -1.736 -1.653 -1.650 -1.569 -1.739 -1.650 -1.695
-1.124 -1.239 -1.357 -1.300 -1.597 -1.241 -1.359 -1.305 -1.632
-1.387 -1.567 -1.736 -1.653 -1.650 -1.569 -1.739 -1.650 -1.695
1.299
1.796
1.299
1.796
1.309
1.786
1.309
1.786
1.1 V
V
C2
CCL
=
4.580 4.985 5.500 5.364 5.576 5.110 5.627 5.491 5.644
1.926 2.014 2.217 2.236 2.155 2.128 2.334 2.352 2.143
4.569 4.973 5.488 5.352 5.564 5.099 5.616 5.480 5.633
1.917 2.005 2.208 2.227 2.146 2.119 2.325 2.343 2.134
4.573 4.978 5.494 5.358 5.570 5.105 5.623 5.487 5.640
1.924 2.013 2.217 2.236 2.155 2.128 2.335 2.353 2.144
4.634 5.027 5.530 5.394 5.578 5.156 5.661 5.525 5.651
1.951 2.030 2.223 2.242 2.160 2.148 2.343 2.360 2.151
4.634 5.027 5.530 5.394 5.578 5.156 5.661 5.525 5.651
1.951 2.030 2.223 2.242 2.160 2.148 2.343 2.360 2.151
1.1 V
list the maximum I/O timing parameters for
V
C2
CCL
=
1.436
2.027
1.436
2.027
1.447
2.016
1.447
2.016
1.1 V
V
C3
CCL
=
1.1 V
V
C3
CCL
=
1.571
2.253
1.571
2.253
1.587
2.237
1.587
2.237
1.1 V
V
C4
CCL
1.1 V
V
=
C4
CCL
=
1.501
2.141
1.501
2.141
1.517
2.125
1.517
2.125
1.1 V
V
CCL
1.1 V
V
=
CCL
C4L
=
C4L
1.798
2.145
1.798
2.145
1.814
2.129
1.814
2.129
0.9 V
V
Stratix III Device Handbook, Volume 2
CCL
0.9 V
V
CCL
=
=
1.446
2.036
1.446
2.036
1.457
2.025
1.457
2.025
1.1 V
V
1.1 V
V
CCL
I3
CCL
I3
=
=
1.583
2.262
1.583
2.262
1.598
2.247
1.598
2.247
1.1 V
1.1 V
V
V
I4
CCL
I4
CCL
=
=
1.1 V
V
1.516
2.145
1.516
2.145
1.531
2.130
1.531
2.130
1.1 V
V
1–217
CCL
CCL
=
=
I4L
I4L
0.9 V
V
1.835
2.193
1.835
2.193
1.850
2.178
1.850
2.178
CCL
0.9 V
V
CCL
=
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns