DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 15

KIT DEVELOPMENT STRATIX III

DK-DEV-3SL150N

Manufacturer Part Number

DK-DEV-3SL150N

Description

KIT DEVELOPMENT STRATIX III

Manufacturer

Altera

Series

Stratix® IIIr

Type

FPGAr

Datasheets

1.EP3SL150F780C4N.pdf (16 pages)

2.EP3SL150F780C4N.pdf (332 pages)

3.DK-DEV-3SL150N.pdf (34 pages)

Specifications of DK-DEV-3SL150N

Contents

Development Platform, Cables and Software

Silicon Manufacturer

Altera

Core Architecture

FPGA

Core Sub-architecture

Stratix

Silicon Core Number

EP3S

Silicon Family Name

Stratix III

Kit Contents

Development Board, Cable And Accessories

Rohs Compliant

Yes

For Use With/related Products

EP3SL150F152

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

544-2568

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Bonase Electronics (HK) Co., Limited

Part Number:

DK-DEV-3SL150N

Manufacturer:

Altera

Quantity:

135

Company:

BOSTOCK HK LIMITED

BOSTOCK HK LIMITED

Part Number:

DK-DEV-3SL150N

Manufacturer:

ALTERA

0

Company:

BOSTOCK HK LIMITED

BOSTOCK HK LIMITED

Part Number:

DK-DEV-3SL150N-0D

Manufacturer:

ALTERA

0

Current page: 15 of 332
Download datasheet (4Mb)

Table 1–20. PLL Specifications for Stratix III Devices (Part 2 of 3)

f

t

t

t

t

t

t

CLBW

PLL_PSERR

ARESET

INCCJ

OUTPJ_DC

OUTCCJ_DC

OUTPJ_IO

Symbol

(3),

(5),

(5)

(5)

(4)

(8)

PLL closed-loop low bandwidth

PLL closed-loop medium

bandwidth

PLL closed-loop high bandwidth

(6)

Accuracy of PLL phase shift

Minimum pulse width on areset

signal

Input clock cycle to cycle jitter

(F

Input clock cycle to cycle jitter

(F

Period Jitter for dedicated clock

output (F

Period Jitter for dedicated clock

output (F

Cycle to Cycle Jitter for dedicated

clock output

(F

Cycle to Cycle Jitter for dedicated

clock output

(F

Period Jitter for clock output on

regular IO (F

Period Jitter for clock output on

regular IO (F

REF

REF

OUT

OUT

 100 MHz)

< 100 MHz)

100 MHz)

< 100 MHz)

OUT

OUT

100 MHz)

< 100 MHz)

Parameter

OUT

OUT

 100 MHz)

< 100 MHz)

Min

—

—

—

—

10

—

—

—

—

—

—

—

—

V

CCL

Typ

= 1.1 V

0.3

1.5

C2

—

—

—

—

—

—

—

—

—

—

4

±750

Max

0.15

17.5

17.5

±50

175

175

600

—

—

—

—

60

Min

—

—

—

—

10

—

—

—

—

—

—

—

—

V

CCL

C3, I3

Typ

= 1.1 V

0.3

1.5

—

—

—

—

—

—

—

—

—

—

4

±750

0.15

17.5

17.5

Max

±50

175

175

600

—

—

—

—

60

Min

—

—

—

—

10

—

—

—

—

—

—

—

—

V

CCL

C4, I4

Typ

0.3

1.5

= 1.1 V

—

—

—

—

—

—

—

—

—

—

4

±750

Max

0.15

17.5

17.5

±50

175

175

600

—

—

—

—

60

Min

—

—

—

—

10

—

—

—

—

—

—

—

—

V

CCL

Typ

= 1.1 V

0.3

1.5

—

—

—

—

—

—

—

—

—

—

4

±750

Max

0.15

17.5

17.5

±50

175

175

600

—

—

—

—

60

C4L, I4L

Min

—

—

—

—

10

—

—

—

—

—

—

—

—

V

CCL

Typ

0.3

1.5

= 0.9 V

—

—

—

—

—

—

—

—

—

—

4

±500 ps (p-p)

Max

22.5

22.5

±50

225

225

750

0.1

—

—

—

—

75

UI (p-p)

ps (p-p)

ps (p-p)

ps (p-p)

(p-p)

(p-p)

(p-p)

Unit

MHz

MHz

MHz

mUI

mUI

mUI

ps

ns

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